Patents by Inventor Makoto Wakita

Makoto Wakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6550050
    Abstract: In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S4: YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S5: YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S5: NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: April 15, 2003
    Assignee: Fujitsu Limited
    Inventors: Toshikatsu Hosono, Takashi Yoneda, Miyako Fujita, Makoto Wakita
  • Publication number: 20020049957
    Abstract: In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S4: YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S5: YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S5: NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared.
    Type: Application
    Filed: March 7, 2001
    Publication date: April 25, 2002
    Inventors: Toshikatsu Hosono, Takashi Yoneda, Miyako Fujita, Makoto Wakita
  • Patent number: 5857164
    Abstract: A system and method for calculating current consumption characteristics of cells of semiconductor circuits is disclosed. According to the invention, the current consumption characteristics of the cells is calculated based on the status changes of the internal memories of the cells. The calculation of current consumption characteristics of cells according to the invention is not only more accurate, but also more efficient in terms of the time needed for logic simulation.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: January 5, 1999
    Assignee: Fujitsu Limited
    Inventor: Makoto Wakita
  • Patent number: 5663889
    Abstract: A delay time computing apparatus includes a data base for storing data on various cells, an input device operable by a designer, and a processing unit coupled to the data base and the input device. The processing unit includes a data input interface, a path building section and a delay time computing section. The data input interface controls transfer of input data from the input device. The path building section reads detailed data on a selected cell from the data base in accordance with circuit redesign data input by a circuit designer to the data input device, and thereby constructs a signal propagation path for cells involved in circuit redesign. Every time the path building section constructs new signal propagation paths, the delay time computing section computes delay times of cells involved in circuit redesign.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: September 2, 1997
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Makoto Wakita
  • Patent number: 5072209
    Abstract: This data display system includes a wireless transmitter mounted on a vehicle. The wireless transmitter is used for transmitting a signal representative of data related to operation of the vehicle. A wireless receiver is mounted on a helmet worn by a driver of the vehicle. The receiver receives a transmitted data signal from the transmitter and generates an output signal. A power supply is mounted on the helmet, and comprises a solar cell and a secondary battery for supplying electric power to the receiver. Converter circuits are connected to an output stage of the wireless receiver for converting the output signal of the receiver into a light display signal of visible rays. A display and mirror are mounted on the helmet for projecting and displaying the display signal from the converter circuits in a forward visual field of the driver.
    Type: Grant
    Filed: January 22, 1990
    Date of Patent: December 10, 1991
    Assignee: Kawajyuu Gifu Engineering Co., Ltd.
    Inventors: Toshio Hori, Kenji Furuhashi, Makoto Wakita, Kazuo Ueda