Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

Abstract: Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

Abstract: An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between the end sections. One or both end sections are wider than the body section, e.g., by approximately 6 nanometers to approximately 12 nanometers. One end section is connected to an interconnect at the backside of the support structure. The other end section is connected to a jumper, which is connected to the source electrode or drain electrode.

Abstract: IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a source or drain (S/D) region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact structure, and a liner material on at least a portion of a sidewall of the gap, the liner material comprising aluminum and oxygen.

Abstract: IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a S/D region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact structure, and a liner material over at least a portion of a sidewall of the region below the contact structure, the liner material comprising aluminum and oxygen.

Abstract: Integrated circuit structures having backside plug last approach are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.

Abstract: Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.

Abstract: Integrated circuit structures having air gaps are described. In an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. A dielectric structure is between adjacent ones of the conductive lines and over the air gaps. A first etch stop layer is on the dielectric structure but not on the conductive lines. A second etch stop layer is on the first etch stop layer and on the conductive lines. A second dielectric layer is above the second etch stop layer. A conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to backside contacts for field effect transistors formed using a backside contact etch prior to cavity spacer formation. A transistor includes semiconductor structures such as nanoribbons extending between a source and a drain. A spacer material is between a gate and the source/drain as cavity spacer fill. The spacer material is also between a portion of a backside contact and a portion of the source/drain, to eliminate a short between the backside contact and the gate.

Abstract: Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Abstract: Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.

Abstract: Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

Abstract: Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

Abstract: Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.

Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.