Abstract: An electronic device comprises a host processor comprising a memory controller connected to a memory device comprising a near memory processing unit. The host processor is configured to detect a system memory shortage for an operation of an operating system (OS), configure a memory region of the memory device for use in a memory pool of the OS in response to the system memory shortage, identify a request to execute an acceleration logic, and configure the memory region of the memory device for direct access by the near memory processing unit in response to the request to execute the acceleration logic.

Abstract: A memory device includes: a memory storing instructions; and a processing unit including one or more processors, wherein the memory device is connected with a host processor through an interface, and wherein, the instructions, when executed by the processing unit, cause the memory device to: select, from among memory blocks stored in the memory, candidate hot memory blocks, the selecting based on access counts of the respective memory blocks stored in the memory; select a hot sub-block based on a number access counts of respective sub-blocks, including the hot sub-block, split from the selected candidate hot memory blocks; and transmit the selected hot sub-block to the host processor, based on a memory command regarding the hot sub-block, wherein the memory command is received from the host processor by the processing unit.

Abstract: A memory device and an operating method of the memory device are disclosed. The memory device includes a memory processor including a plurality of processing units (PUs) and a processor controller configured to control the plurality of PUs and a memory controller configured to communicate with the processor controller and control first memory banks. The memory processor is configured to determine, based on a type of an operation performed by the memory processor, a read scheme by which the memory controller reads second data stored in second memory banks of a host device into the first memory banks as first data for the memory processor.

Abstract: A memory system includes a host and a memory device. The host is configured to translate a virtual address into first physical address based on a first page size and issue a memory access request including the first physical address. The memory device is configured to receive the memory access request from the host, translate the first physical address into a second physical address based on a second page size that is smaller than the first page size in response to the memory request, and access memory cells using the second physical address.

Abstract: An electronic device comprises a host processor comprising a memory controller connected to a memory device comprising a near memory processing unit. The host processor is configured to detect a system memory shortage for an operation of an operating system (OS), configure a memory region of the memory device for use in a memory pool of the OS in response to the system memory shortage, identify a request to execute an acceleration logic, and configure the memory region of the memory device for direct access by the near memory processing unit in response to the request to execute the acceleration logic.

Abstract: A neural network operation method and apparatus are disclosed, where the network operation method including receiving data for a neural network operation, determining whether a size of the data is less than or equal to a threshold, generating stacked data by stacking a portion of the data based on the determining, and performing the neural network operation in parallel based on the stacked data.