Patents by Inventor Malati Hedge

Malati Hedge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7049193
    Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: May 23, 2006
    Assignee: Infineon Technologies AG
    Inventors: Michael Maldei, Jinhwan Lee, Guenter Gerstmeier, Brian Cousineau, Jon S. Berry, II, Steven M. Baker, Malati Hedge
  • Publication number: 20050062111
    Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.
    Type: Application
    Filed: October 7, 2004
    Publication date: March 24, 2005
    Inventors: Michael Maldei, Jinhwan Lee, Guenter Gerstmeier, Brian Cousineau, Jon Berry, Steven Baker, Malati Hedge
  • Patent number: 6822301
    Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: November 23, 2004
    Assignee: Infineon Technologies AG
    Inventors: Michael Maldei, Jinhwan Lee, Guenter Gerstmeier, Brian Cousineau, Jon S. Berry, II, Steven M. Baker, Malati Hedge
  • Publication number: 20040021154
    Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 5, 2004
    Applicant: Infineon Technologies North America Corp.
    Inventors: Michael Maldei, Jinhwan Lee, Guenter Gerstmeier, Brian Cousineau, Jon S. Berry, Steven M. Baker, Malati Hedge