Patents by Inventor Malay Ganai
Malay Ganai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9721057Abstract: A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The NCDC receives and stores netlist corrections from user input or automatically corrects certain CDC violations, in the netlist.Type: GrantFiled: July 2, 2015Date of Patent: August 1, 2017Assignee: Synopsys, Inc.Inventors: Malay Ganai, Mohamed Shaker Sarwary, Maher Mneimneh, Paras Mal Jain, Mohammad Homayoun Movahed-Ezazi, Pronay Kumar Biswas, Nishant Gupta
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Publication number: 20160259879Abstract: A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The NCDC receives and stores netlist corrections from user input or automatically corrects certain CDC violations, in the netlist.Type: ApplicationFiled: July 2, 2015Publication date: September 8, 2016Applicant: Synopsys, Inc.Inventors: Malay Ganai, Mohamed Shaker Sarwary, Maher Mneimneh, Paras Mal Jain, Mohammad Homayoun Movahed-Ezazi, Pronay Kumar Biswas, Nishant Gupta
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Publication number: 20150081243Abstract: Disclosed are a testing framework—SETSUD ?—that uses perturbation-based exploration for robustness testing of modern scalable distributed systems. In sharp contrast to existing testing techniques and tools that are limited in that they are typically based on black-box approaches or they focus mostly on failure recovery testing, SETSUD ? is a flexible framework to exercise various perturbations to create stressful scenarios. SETSUD ? is built on an underlying instrumentation infrastructure that provides abstractions of internal states of the system as labeled entities. Both novice and advanced testers can use these labeled entities to specify scenarios of interest at the high level, in the form of a declarative style test policy. SETSUD ? automatically generates perturbation sequences and applies them to system-level implementations, without burdening the tester with low-level details.Type: ApplicationFiled: March 18, 2014Publication date: March 19, 2015Applicant: NEC Laboratories America, Inc.Inventors: Malay Ganai, Gogul Balakrishnan, Pallavi Joshi, Aarti Gupta
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Patent number: 8707272Abstract: A computer implemented testing methodology employing a scenario-driven modeling of specific instances of bug patterns that commonly occur in concurrent programs which encodes these instances in an SMT-based symbolic analysis. Such modeling and encoding advantageously allow the symbolic analysis framework to focus on real bugs, thereby allowing effective utilization of resources. Experimentation determined a number of previously unknown bugs in public benchmarks and advantageously scenario-specific modeling and encoding improves the scalability of symbolic technique and, therefore, improves overall quality of concurrency testing.Type: GrantFiled: January 4, 2012Date of Patent: April 22, 2014Assignee: NEC Laboratories America, Inc.Inventor: Malay Ganai
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Publication number: 20140108867Abstract: Disclosed is a dynamic taint analysis framework for multithreaded programs (DTAM) that identifies a subset of program inputs and shared memory accesses that are relevant for issues related to concurrency. Computer implemented methods according to the framework generally involve the computer implemented steps of: applying independently a dynamic taint analysis to each of the multiple threads comprising a multi-threaded computer program; aggregating each independent result from the analysis for each of the multiple threads by consolidating effect of taint analysis in one or more possible re-orderings of observed shared memory accesses among threads; and outputting an indicia of the aggregated result as a set of relevant program inputs or a set of relevant shared memory accesses.Type: ApplicationFiled: March 13, 2013Publication date: April 17, 2014Applicant: NEC LABORATORIES AMERICA, INC.Inventors: Malay Ganai, Dongyoon Lee, Aarti Gupta
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Patent number: 8504330Abstract: A system and method for bounded model checking of computer programs includes decomposing a program having at least one reachable property node for bounded model checking (BMC) into sub-problems by employing a tunneling and slicing-based (TSR) BMC reduction method. The sub-problems of the TSR method are partitioned in a distributed environment, where the distributed environment includes at least one master processing unit and at least one client unit. The sub-problems are solved by each client independently of other clients to reduce communication overhead and provide scalability.Type: GrantFiled: September 24, 2008Date of Patent: August 6, 2013Assignee: NEC Laboratories America, Inc.Inventor: Malay Ganai
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Publication number: 20120174074Abstract: A computer implemented testing methodology employing a scenario-driven modeling of specific instances of bug patterns that commonly occur in concurrent programs which encodes these instances in an SMT-based symbolic analysis. Such modeling and encoding advantageously allow the symbolic analysis framework to focus on real bugs, thereby allowing effective utilization of resources. Experimentation determined a number of previously unknown bugs in public benchmarks and advantageously scenario-specific modeling and encoding improves the scalability of symbolic technique and, therefore, improves overall quality of concurrency testing.Type: ApplicationFiled: January 4, 2012Publication date: July 5, 2012Applicant: NEC LABORATORIES AMERICA, INC.Inventor: Malay GANAI
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Publication number: 20120151271Abstract: A computer implemented testing framework for symbolic trace analysis of observed concurrent traces that uses MAT-based reduction to obtain succinct encoding of concurrency constraints, resulting in quadratic formulation in terms of number of transitions. We also present encoding of various violation conditions. Especially, for data races and deadlocks, we present techniques to infer and encode the respective conditions. Our experimental results show the efficacy of such encoding compared to previous encoding using cubic formulation. We provided proof of correctness of our symbolic encoding.Type: ApplicationFiled: December 9, 2011Publication date: June 14, 2012Applicant: NEC Laboratories America, Inc.Inventor: Malay GANAI
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Patent number: 8131532Abstract: A system and method is disclosed for formal verification of software programs that advantageously bounds the ranges of values that a variable in the software can take during runtime.Type: GrantFiled: June 3, 2006Date of Patent: March 6, 2012Assignee: NEC Laboratories America, Inc.Inventors: Srihari Cadambi, Aleksandr Zaks, Franjo Ivancic, Ilya Shlyakhter, Zijiang Yang, Malay Ganai, Aarti Gupta, Pranav Ashar
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Publication number: 20110246970Abstract: A method for the verification of multi-threaded computer programs through the use of concurrent trace programs (CTPs) and transaction sequence graphs (TSGs).Type: ApplicationFiled: March 30, 2011Publication date: October 6, 2011Applicant: NEC LABORATORIES AMERICA, INC.Inventors: Malay GANAI, Chao WANG
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Patent number: 8005661Abstract: A computer implemented method for modeling and verifying concurrent systems which uses Satisfiability-Modulo Theory (SMT)-based Bounded Model Checking (BMC) to detect violations of safety properties such as data races. A particularly distinguishing aspect of our inventive method is that we do not introduce wait-cycles in our symbolic models for the individual threads, which are typically required for considering an interleaved execution of the threads. These wait-cycles are detrimental to the performance of BMC. Instead, we first create independent models for the different threads, and add inter-model constraints lazily, incrementally, and on-the-fly during BMC unrolling to capture the sequential consistency and synchronization semantics. We show that our constraints provide a sound and complete modeling with respect to the considered semantics.Type: GrantFiled: May 7, 2008Date of Patent: August 23, 2011Assignee: NEC Laboratories America, Inc.Inventors: Malay Ganai, Aarti Gupta
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Patent number: 7930659Abstract: A system and method is disclosed for formal verification of software programs that advantageously improves performance of an abstraction-refinement loop in the verification system.Type: GrantFiled: June 3, 2006Date of Patent: April 19, 2011Assignee: NEC Laboratories America, Inc.Inventors: Franjo Ivancic, Aarti Gupta, Malay Ganai, Himanshu Jain
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Patent number: 7853906Abstract: An accelerated High-Level Bounded Model Checking method that efficiently extracts high-level information from the model, uses that extracted information to obtain an improved verification model, and applies relevant information on-the-fly to simplify the BMC-problem instances.Type: GrantFiled: March 22, 2007Date of Patent: December 14, 2010Assignee: NEC Laboratories America, Inc.Inventors: Malay Ganai, Aarti Gupta
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Publication number: 20100281469Abstract: A symbolic predictive analysis method for finding assertion violations and atomicity violations in concurrent programs is shown that derives a concurrent trace program (CTP) for a program under a given test. A logic formula is then generated based on a concurrent static single assignment (CSSA) representation of the CTP, including at least one assertion property or atomicity violation. The satisfiability of the formula is then determined, such that the outcome of the determination indicates an assertion/atomicity violation.Type: ApplicationFiled: March 18, 2010Publication date: November 4, 2010Applicant: NEC Laboratories America, Inc.Inventors: Chao Wang, Malay Ganai, Aarti Gupta
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Publication number: 20100251222Abstract: A computer implemented method for obtaining a completeness threshold (CT) in Bounded Model Checking systems for software programs.Type: ApplicationFiled: March 24, 2009Publication date: September 30, 2010Applicant: NEC Laboratories AmericaInventor: Malay Ganai
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Patent number: 7742907Abstract: A method of obtaining a resolution-based proof of unsatisfiability using a SAT procedure for a hybrid Boolean constraint problem comprising representing constraints as a combination of clauses and interconnected gates. The proof is obtained as a combination of clauses, circuit gates and gate connectivity constraints sufficient for unsatisfiability.Type: GrantFiled: January 23, 2004Date of Patent: June 22, 2010Assignee: NEC Laboratories America, Inc.Inventors: Aarti Gupta, Malay Ganai, Zijiang Yang, Pranav Ashar
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Patent number: 7743352Abstract: Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose functional units from “verification friendly” library; 6) Re-use operations; 7) Perform property-preserving slicing; 8) Support “assume” and “assert” in the language specification; and 8) Use external memory modules instead of register arrays.Type: GrantFiled: March 22, 2007Date of Patent: June 22, 2010Assignee: NEC Laboratories America, Inc.Inventors: Malay Ganai, Aarti Gupta
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Patent number: 7711525Abstract: A method for bounded model checking of arbitrary Linear Time Logic temporal properties. The method comprises translating properties associated with temporal operators F(p), G(p), U(p, q) and X(p) into property checking schemas comprising Boolean satisfiability checks, wherein F represents an eventuality operator, G represents a globally operator, U represents an until operator and X represents a next-time operator. The overall property is checked in a customized manner by repeated invocations of the property checking schemas for F(p), G(p), U(p, q), X(p) operators and standard handling of atomic propositions and Boolean operators.Type: GrantFiled: May 30, 2002Date of Patent: May 4, 2010Assignee: NEC CorporationInventors: Malay Ganai, Lintao Zhang, Aarti Gupta, Zijiang Yang, Pranav Ashar
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Publication number: 20100011057Abstract: A system and method for bounded model checking of computer programs includes decomposing a program having at least one reachable property node for bounded model checking (BMC) into sub-problems by employing a tunneling and slicing-based (TSR) BMC reduction method. The sub-problems of the TSR method are partitioned in a distributed environment, where the distributed environment includes at least one master processing unit and at least one client unit. The sub-problems are solved by each client independently of other clients to reduce communication overhead and provide scalability.Type: ApplicationFiled: September 24, 2008Publication date: January 14, 2010Applicant: NEC Laboratories America, Inc.Inventor: MALAY GANAI
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Publication number: 20080281563Abstract: A computer implemented method for modeling and verifying concurrent systems which uses Satisfiability-Modulo Theory (SMT)-based Bounded Model Checking (BMC) to detect violations of safety properties such as data races. A particularly distinguishing aspect of our inventive method is that we do not introduce wait-cycles in our symbolic models for the individual threads, which are typically required for considering an interleaved execution of the threads. These wait-cycles are detrimental to the performance of BMC. Instead, we first create independent models for the different threads, and add inter-model constraints lazily, incrementally, and on-the-fly during BMC unrolling to capture the sequential consistency and synchronization semantics. We show that our constraints provide a sound and complete modeling with respect to the considered semantics.Type: ApplicationFiled: May 7, 2008Publication date: November 13, 2008Applicant: NEC LABORATORIES AMERICAInventors: Malay GANAI, Aarti GUPTA