Abstract: A processor array 100 having an improved I/O pin utilization scheme. The inventive processor array 100 includes a first and a second set of processors 112 and 114 arranged within a chip boundary B1, with each of the processors 112 within the first set being positioned adjacent the chip boundary B1. The invention further includes an I/O arrangement for providing a plurality of electrical paths 136 across the chip boundary B1. A switch network is included for connecting each of the I/O paths 136 to a horizontal port 130 of an associated one of the processors 112 within the first set during a first clock cycle and for connecting each of the I/O paths 136 to a vertical communication port 132 of the associated processor during a second clock cycle.

Abstract: A mesh processor array including a plurality of one-bit processor cells arranged in a matrix. Each processor receives inputs from adjacent processors or external sources and performs a logical function involving its own present state and the inputs thereto. Control circuitry provides control information indicative of a logical function to be performed to each of the processors in parallel, and pattern selection circuitry enables selected ones of the processors to respond to the control information.