Patents by Inventor Malcolm Bevan

Malcolm Bevan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161171
    Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.
    Type: Application
    Filed: September 23, 2019
    Publication date: May 21, 2020
    Inventors: Benjamin COLOMBEAU, Theresa Kramer GUARINI, Malcolm BEVAN, Rui CHENG
  • Publication number: 20200144397
    Abstract: Methods and apparatuses for processing substrates, such as during silicon-germanium pre-cleans, are provided. A method includes introducing the substrate into a processing system, where the substrate contains a plurality of silicon-containing (e.g., SiGe) fins and a contaminant disposed on the silicon-containing fins, and exposing the substrate to a plasma treatment to remove at least a portion of the contaminant disposed from the silicon-containing fins. The method also includes exposing the substrate to an oxidation treatment to produce an oxide layer on the silicon-containing fins and the remaining contaminant thereon, then exposing the substrate to a dry-clean treatment to remove the oxide layer and the remaining contaminant from the silicon-containing fins and produce a cleaned surface thereon, and depositing an epitaxial layer on the cleaned surface on the silicon-containing fins.
    Type: Application
    Filed: September 17, 2019
    Publication date: May 7, 2020
    Applicants: Applied Materials, Inc., Applied Materials, Inc.
    Inventors: Abhishek DUBE, Sheng-Chin KUNG, Malcolm BEVAN, Johanes SWENBERG
  • Publication number: 20200111659
    Abstract: A method of modifying a layer in a semiconductor device is provided. The method includes depositing a low quality film on a semiconductor substrate, and exposing a surface of the low quality film to a first process gas comprising helium while the substrate is heated to a first temperature, and exposing a surface of the low quality film to a second process gas comprising oxygen gas while the substrate is heated to a second temperature that is different than the first temperature. The electrical properties of the film are improved by undergoing the aforementioned processes.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: Wei LIU, Theresa Kramer GUARINI, Linlin WANG, Malcolm BEVAN, Johanes S. SWENBERG, Vladimir NAGORNY, Bernard L. HWANG, Kin Pong LO, Lara HAWRYLCHAK, Rene GEORGE
  • Publication number: 20190385825
    Abstract: Embodiments described herein generally relate to a method and apparatus for fabricating a chamber component for a plasma process chamber. In one embodiment a chamber component used within a plasma processing chamber is provided that includes a metallic base material comprising a roughened non-planar first surface, wherein the roughened non-planar surface has an Ra surface roughness of between 4 micro-inches and 80 micro-inches, a planar silica coating formed over the roughened non-planar surface, wherein the planar silica coating has a surface that has an Ra surface roughness that is less than the Ra surface roughness of the roughened non-planar surface, a thickness between about 0.2 microns and about 10 microns, less than 1% porosity by volume, and contains less than 2E12 atoms/centimeters2 of aluminum.
    Type: Application
    Filed: May 21, 2019
    Publication date: December 19, 2019
    Inventors: Jian WU, Wei LIU, Theresa Kramer GUARINI, Linlin WANG, Malcolm BEVAN, Lara HAWRYLCHAK
  • Patent number: 10290504
    Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 14, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Theresa Kramer Guarini, Huy Q. Nguyen, Malcolm Bevan, Houda Graoui, Philip A. Bottini, Bernard L. Hwang, Lara Hawrylchak, Rene George
  • Publication number: 20190088485
    Abstract: Embodiments of the disclosure provide an improved apparatus and methods for nitridation of stacks of materials. In one embodiment, a method for processing a substrate in a processing region of a process chamber is provided. The method includes generating and flowing plasma species from a remote plasma source to a delivery member having a longitudinal passageway, flowing plasma species from the longitudinal passageway to an inlet port formed in a sidewall of the process chamber, wherein the plasma species are flowed at an angle into the inlet port to promote collision of ions or reaction of ions with electrons or charged particles in the plasma species such that ions are substantially eliminated from the plasma species before entering the processing region of the process chamber, and selectively incorporating atomic radicals from the plasma species in silicon or polysilicon regions of the substrate.
    Type: Application
    Filed: August 13, 2018
    Publication date: March 21, 2019
    Inventors: Matthew Scott ROGERS, Roger CURTIS, Lara HAWRYLCHAK, Ken Kaung LAI, Bernard L. HWANG, Jeffrey TOBIN, Christopher S. OLSEN, Malcolm BEVAN
  • Publication number: 20180082847
    Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventors: Wei LIU, Theresa Kramer GUARINI, Huy Q. NGUYEN, Malcolm BEVAN, Houda GRAOUI, Philip A. BOTTINI, Bernard L. HWANG, Lara HAWRYLCHAK, Rene GEORGE
  • Patent number: 9831091
    Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: November 28, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Theresa Kramer Guarini, Huy Q. Nguyen, Malcolm Bevan, Houda Graoui, Philip A. Bottini, Bernard L. Hwang, Lara Hawrylchak, Rene George
  • Publication number: 20160358781
    Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 8, 2016
    Inventors: Wei LIU, Theresa Kramer GUARINI, Huy Q. NGUYEN, Malcolm BEVAN, Houda GRAOUI, Philip A. BOTTINI, Bernard L. HWANG, Lara HAWRYLCHAK, Rene GEORGE
  • Publication number: 20080050882
    Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 28, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Malcolm Bevan, Haowen Bu, Hiroaki Niimi, Husam Alshareef
  • Publication number: 20060183337
    Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.
    Type: Application
    Filed: January 31, 2006
    Publication date: August 17, 2006
    Inventors: Brian Kirkpatrick, Rajesh Khamankar, Malcolm Bevan, April Gurba, Husam Alshareef, Clinton Montgomery, Mark Somervell
  • Publication number: 20060084229
    Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.
    Type: Application
    Filed: December 2, 2005
    Publication date: April 20, 2006
    Inventors: Brian Kirkpatrick, Rajesh Khamankar, Malcolm Bevan, April Gurba, Husam Alshareef, Clinton Montgomery, Mark Somervell
  • Publication number: 20060046514
    Abstract: A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Husam Alshareef, Rajesh Khamankar, Ajith Varghese, Cathy Chancellor, Anand Krishnan, Malcolm Bevan
  • Publication number: 20050221564
    Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
    Type: Application
    Filed: June 6, 2005
    Publication date: October 6, 2005
    Inventors: Malcolm Bevan, Haowen Bu, Hiroaki Niimi, Husam Alshareef
  • Publication number: 20050205948
    Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.
    Type: Application
    Filed: April 28, 2005
    Publication date: September 22, 2005
    Inventors: Antonio Rotondaro, Luigi Colombo, Malcolm Bevan
  • Publication number: 20050136589
    Abstract: Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.
    Type: Application
    Filed: December 17, 2003
    Publication date: June 23, 2005
    Inventors: Antonio Rotondaro, Douglas Mercer, Luigi Colombo, Mark Visokay, Haowen Bu, Malcolm Bevan