Patents by Inventor Malcolm Carroll

Malcolm Carroll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10929769
    Abstract: A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 23, 2021
    Assignees: SOCPRA SCIENCES ET GÉNIE S.E.C., NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC.
    Inventors: Michel Pioro-Ladriere, Sophie Rochette, John King Gamble, Gregory A Ten Eyck, Martin Rudolph, Malcolm Carroll
  • Publication number: 20190130298
    Abstract: A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.
    Type: Application
    Filed: June 8, 2017
    Publication date: May 2, 2019
    Inventors: Michel PIORO-LADRIERE, Sophie ROCHETTE, John KING GAMBLE, Gregory A TEN EYCK, Martin RUDOLPH, Malcolm CARROLL
  • Patent number: 7297569
    Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: November 20, 2007
    Assignee: Noble Device Technologies Corporation
    Inventors: Jeff Devin Bude, Malcolm Carroll, Clifford Alan King
  • Publication number: 20060057825
    Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all
    Type: Application
    Filed: November 8, 2005
    Publication date: March 16, 2006
    Applicant: Agere Systems Inc.
    Inventors: Jeffrey Bude, Malcolm Carroll, Clifford King
  • Patent number: 7012314
    Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: March 14, 2006
    Assignee: Agere Systems Inc.
    Inventors: Jeffrey Devin Bude, Malcolm Carroll, Clifford Alan King
  • Publication number: 20040121507
    Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all
    Type: Application
    Filed: June 3, 2003
    Publication date: June 24, 2004
    Inventors: Jeffrey Devin Bude, Malcolm Carroll, Clifford Alan King