Abstract: In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address space, the virtual group address component is input to a contents addressable memory (767), which outputs a group code (767), and the group code and virtual page address component (768X,Y) are input to a RAM page table (750) which outputs the page address. When the physical memory capacity is substantially smaller than the virtual address space, the CAM provides a large saving in page table size. In the case where the data-elements provide a plural-dimensional representation, for example as in pixel data, the pages include data elements which are contiguous in each of the plural dimensions in order to reduce the amount of page-swapping between the physical memory and a paging memory. The data-elements in the physical memory are accessible in parallel as contiguous patches.

Abstract: A system for storing and processing an array of data-elements formatted as a plurality of pages of the data elements, and especially for use in a demand-paged dual memory system, comprises a memory in which each memory location has a capacity of, for example, 32 bits and a processing means for processing data elements and reading the data elements from and/or writing them to the memory. In order to enable full use to be made of the memory and to facilitate the use of demand-paging when dealing with data-elements having less bits, for example 16 or 8 bits, a plurality of such data-elements are stored at different bit levels in each memory location so that at no memory location is there stored data-elements from more than one page.

Abstract: A system and method stores fonts and generates characters. Instead of the fonts containing bit maps, the storage area (116) for each character contains the addresses (GPCR Addresses) of instructions to be used to form the character, and the required parameters for those instructions. In a preferred embodiment, a lookup table (114) for the font contains, for each character, the address of the code to start executing and details of how much more information is stored for this character and where to find it. For each character, the stored information includes addresses of microcode instructions (126) followed by the required number of parameters to define the actions necessary for character generation.

Abstract: The present invention is a system architecture and methods of operation which reaps all the advantages of patch access processing while allowing many important types of image manipulation to be performed to the granularity and addressability of a single pixel. It goes beyond conventional concepts of the limits of pixel granularity by manipulating pixel data across and within bit planes in a manner which enables bit positions to be exchanged within the same pixel and/or swapped between different pixels.

Abstract: A system and method of merging and manipulating pixel information for display on a raster scan monitor is disclosed. The invention operates at speeds imperceptible to the viewer by collecting, in each memory access cycle, the data representing multiple pixels and by performing merge and manipulation functions on pixel groups at video rate under control of control data from a state machine. The state machine allows for unique processing decisions to be made for every pixel group displayed on the monitor.

Abstract: A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor.One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus.

Abstract: A crossbar converter to format 32 bit raster formatted I/O data into 5.times.4 patch formatted eight bit pixel data enables a 160 bit wide pixel data bus to be used so as to attain a high bandwidth for I/O devices. By using the wide pixel data bus and patch format for I/O, the facilities of the an screen memory and an arbitrary shape clipper can be made available to process a real time video window on a high resolution, bit mapped display monitor. The crossbar converter can be used to convert the parallel input of standard I/O devices into patch format, (five by four by eight, for example). The thus converted I/O data may be used by an off screen memory and an arbitrary shape clipper at high transfer rates.

Abstract: A system and method for merging two or more analog video signals under control of a third analog video signal. A standard video output from one processor's video signal digital to analog converter (DAC) is used as the control signal for the merging of two or more other video signals. This enables the video outputs of even highly diverse processing schemes to be easily merged. In its preferred embodiment, the system includes analog switching circuitry which is used to mix the video outputs from two or more different systems. The system also includes circuitry which converts the standard video output from a third processor into a large swing TTL signal which is used to control the analog switch.