Patents by Inventor Malcolm Mandviwalla

Malcolm Mandviwalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8631210
    Abstract: Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventors: Adrian C. Moga, Malcolm Mandviwalla, Vedaraman Geetha, Herbert H. Hum
  • Publication number: 20130185522
    Abstract: Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed.
    Type: Application
    Filed: March 5, 2013
    Publication date: July 18, 2013
    Inventors: ADRIAN C. MOGA, MALCOLM MANDVIWALLA, VEDARAMAN GEETHA, HERBERT H. HUM
  • Patent number: 8392665
    Abstract: Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Adrian C. Moga, Malcolm Mandviwalla, Vedaraman Geetha, Herbert H. Hum
  • Patent number: 8055851
    Abstract: In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in an affinity corresponding to the cache.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: November 8, 2011
    Assignee: Intel Corporation
    Inventors: Meenakshisundaram R. Chinthamani, Kai Cheng, Malcolm Mandviwalla, Bahaa Fahim, Keith R. Pflederer
  • Patent number: 8041898
    Abstract: The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. The method may further include protecting said memory slice from cache coherency violations via a home agent configured to transmit and receive data from said memory slice, said home agent configured to store a copy of said presence vector. The method may also include receiving a request for a block of data from at least one processing node at said home agent and comparing said presence vector with said copy of said presence vector stored in said home agent. The method may additionally include eliminating a write update operation between said home agent and said directory if said presence vector and said copy are equivalent. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: October 18, 2011
    Assignee: Intel Corporation
    Inventors: Adrian Moga, Rajat Agarwal, Malcolm Mandviwalla
  • Patent number: 7962694
    Abstract: In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in a snoop filter in accordance with one of the following, if there is a cache miss: at the cache entry location of a corresponding affinity in the snoop filter if the cache entry location is found in the corresponding affinity, or at a derived cache entry location of the corresponding affinity if the cache entry location is not found in the corresponding affinity.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Meenakshisundaram R. Chinthamani, Kai Cheng, Malcolm Mandviwalla, Bahaa Fahim, Keith R. Pflederer
  • Publication number: 20090276581
    Abstract: The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. The method may further include protecting said memory slice from cache coherency violations via a home agent configured to transmit and receive data from said memory slice, said home agent configured to store a copy of said presence vector. The method may also include receiving a request for a block of data from at least one processing node at said home agent and comparing said presence vector with said copy of said presence vector stored in said home agent. The method may additionally include eliminating a write update operation between said home agent and said directory if said presence vector and said copy are equivalent. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: May 1, 2008
    Publication date: November 5, 2009
    Applicant: INTEL CORPORATION
    Inventors: Adrian Moga, Rajat Agarwal, Malcolm Mandviwalla
  • Publication number: 20080147986
    Abstract: In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in an affinity corresponding to the cache.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 19, 2008
    Inventors: Sundaram Chinthamani, Kai Cheng, Malcolm Mandviwalla, Bahaa Fahim, Keith R. Pflederer
  • Publication number: 20070233966
    Abstract: In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in a snoop filter in accordance with one of the following, if there is a cache miss: at the cache entry location of a corresponding affinity in the snoop filter if the cache entry location is found in the corresponding affinity, or at a derived cache entry location of the corresponding affinity if the cache entry location is not found in the corresponding affinity.
    Type: Application
    Filed: December 14, 2006
    Publication date: October 4, 2007
    Inventors: Sundaram Chinthanmani, Kal Cheng, Malcolm Mandviwalla, Bahaa Fahim, Keith R. Pflederer