Patents by Inventor Malcolm Scott Ware

Malcolm Scott Ware has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9298249
    Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Andrew Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8990831
    Abstract: A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8510749
    Abstract: A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8457805
    Abstract: A method, system, and computer usable program product for power distribution considering cooling nodes in a data processing environment. A power demand of a data processing environment is determined for a period. The data processing environment includes a set of computing nodes and cooling nodes. A determination is made that the power demand will exceed a limit on electrical power available to the data processing environment for the period if the computing nodes and the cooling nodes in the data processing environment are operated in a first configuration. A first amount of power is redistributed from a cooling node in the data processing environment to a computing node in the data processing environment such that a temperature related performance threshold of a subset of computing nodes is at least met.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Andreas Bieswanger, Andrew Geissler, Raymond J Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8452991
    Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Andrew Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Publication number: 20120227048
    Abstract: A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 6, 2012
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Publication number: 20110296423
    Abstract: A method, system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: ELMOOTAZBELLAH NABIL ELNOZAHY, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8055477
    Abstract: A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Chase, Soraya Ghiasi, Michael Stephen Floyd, Joshua David Friedrich, Steven Paul Hartman, Norman Karl James, Malcolm Scott Ware, Richard L. Willaman
  • Publication number: 20110257802
    Abstract: A method, system, and computer usable program product for power distribution considering cooling nodes in a data processing environment. A power demand of a data processing environment is determined for a period. The data processing environment includes a set of computing nodes and cooling nodes. A determination is made that the power demand will exceed a limit on electrical power available to the data processing environment for the period if the computing nodes and the cooling nodes in the data processing environment are operated in a first configuration. A first amount of power is redistributed from a cooling node in the data processing environment to a computing node in the data processing environment such that a temperature related performance threshold of a subset of computing nodes is at least met.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Inventors: ANDREAS BIESWANGER, Andrew J. Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8015566
    Abstract: A data processing system attributes energy consumption to individual program segments or threads includes a processor that executes a first thread during a first portion of a measurement interval and a second thread during a second portion of the interval. An energy monitor measures the total energy during the interval. Energy attribution code attributes a first amount of the total energy to the first thread and a second amount to the second thread based in part on the execution times of the threads. The code may define a range of possible energy values by determining maximum and minimum energy constraints for the threads. The invention may also be extended to a multiprocessor environment and to a simultaneous multithreading (SMT) processor. In addition, the process may be expanded to determine energy consumed by various peripheral units such as hard disk controllers and the like.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: September 6, 2011
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Charles R. Lefurgy, Malcolm Scott Ware
  • Patent number: 7958311
    Abstract: Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Richard Edward Matick, Jaime H. Moreno, Malcolm Scott Ware
  • Publication number: 20110047350
    Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.
    Type: Application
    Filed: August 20, 2009
    Publication date: February 24, 2011
    Applicant: International Buisness Machines Corporation
    Inventors: Andrew Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 7873855
    Abstract: A method and system and calibration technique for power measurement and management over multiple time frames provides responsive power control while meeting global system power consumption and power dissipation limits. Power output of one or more system power supplies is measured and processed to produce power values over multiple differing time frames. The measurements from the differing time frames are used to determine whether or not system power consumption should be adjusted and then one or more devices is power-managed in response to the determination. The determination may compare a set of maximum and/or minimum thresholds to each of the measurements from the differing time frames. A calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor calibration is made at the common mode voltage of the power supply output.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dhruv Manmohandas Desai, Nickolas J. Gruendler, Carl A. Morrell, Gary R. Shippy, Michael Leo Scollard, Michael Joseph Steinmetz, Malcolm Scott Ware, Christopher L. Wood
  • Patent number: 7870341
    Abstract: Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Richard Edward Matick, Jaime H. Moreno, Malcolm Scott Ware
  • Patent number: 7818696
    Abstract: A method for estimating power dissipated by a processor core processing a workload-includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Tejas S. Karkhanis, Srinivasan Ramani, Malcolm Scott Ware, Ken Vu
  • Patent number: 7792597
    Abstract: In one embodiment, a control system supports an unlimited number of feedback control loops all sharing control of a component. A component performance rate or “speed” is used as a common metric for negotiating control of the component. Each control loop continuously monitors a system parameter it is tasked with regulating, compares it to a setpoint for that system parameter, and “requests” a speed in relation to the deviation of the associated system parameter from the corresponding setpoint. A controller receives the requested speeds as dynamic inputs and selects one of the requested speeds according to predefined selection logic. The controller communicates the selected speed to an actuator, which causes the component to operate at the selected speed. In this manner, the control system in effect negotiates control of the component in a way that ensures that all of the system parameters are being managed within safe limits.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Brey, Wesley Michael Felter, Sumeet Kochar, Charles Robert Lefurgy, Malcolm Scott Ware, Christopher Landon Wood
  • Patent number: 7779276
    Abstract: Systems and methods are provided for managing power in a processing system. In one embodiment, a target system having a plurality of electronic devices is operated within a net power limit. A local controller detects power consumption for each device, and communicates the power consumption to a power management module. The power management module dynamically apportions the net power limit among the devices, and communicates the apportioned power limit for each device back to the associated local controller. Each local controller enforces the apportioned power limit to an associated device on behalf of the power management module.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Joseph Edward Bolan, Keith Manders Campbell, Vijay Kumar, Malcolm Scott Ware
  • Publication number: 20100125436
    Abstract: A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Applicant: International Business Machines Corporation
    Inventors: Harold W. Chase, Soraya Ghiasi, Michael Stephen Floyd, Joshua David Friedrich, Steven Paul Hartman, Norman Karl James, Malcolm Scott Ware, Richard L. Willaman
  • Publication number: 20090182951
    Abstract: Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed.
    Type: Application
    Filed: May 30, 2008
    Publication date: July 16, 2009
    Applicant: International Business Machines Corporation
    Inventors: Richard Edward Matick, Jaime H. Moreno, Malcolm Scott Ware
  • Patent number: 7536577
    Abstract: A calibration technique provides for precision calibration of system power measurement. The calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor. Calibration measurements are thereby made for voltages substantially equal to the voltage of the power supply output, so that differential measurements are made at substantially the same common-mode voltage by appropriate selection of the relationship of the resistance of the precision reference resistor and the resistance of the sense resistor, where the common-mode voltage of the measurement is substantially equal to the power supply output voltage.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: Dhruv Manmohandas Desai, Nickolas J. Gruendler, Carl A. Morrell, Gary R. Shippy, Michael Leo Scollard, Michael Joseph Steinmetz, Malcolm Scott Ware, Christopher L. Wood