Abstract: Embodiments of an image cognition processing system are provided, including a method that includes detecting an object in a first field of view of a first image sensor, wherein the first image sensor is coupled to a first image cognition processor; generating tracking metadata for the object, wherein the generating is performed by the first image cognition processor, and the tracking metadata describes movement of the object; determining that the object is moving toward a second field of view of a second image sensor, wherein the second image sensor is located adjacent to the first image sensor; and providing the tracking metadata for the object to a second image cognition processor coupled to the second image sensor.

Abstract: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.

Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

Abstract: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.

Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

Abstract: An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.

Abstract: A data processor apparatus comprises a plurality of data receiving means each for receiving data from a data source; a computational element coupleable to each of said data receiving means for performing an operation on said data; and a controller for controlling the flow of data from each data receiving means to the computational element.

Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of memories, an interface for controlling access to the memories by a device, and an identifier identifying at least a memory location in one memory and a memory location in another memory. The interface is responsive to the identifier to condition the memory locations for receiving data and/or for transferring data therefrom. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each processor unit (PU), which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of processor units couplable to receive data from the memory, and control means for controlling transmission of data from the control means to each processor unit. The control means for controlling operations of the data processor units is arranged to transmit data intended for each processor unit (i.e. broadcast data) to the memory, and is adapted to control each processor unit to receive the broadcast data from the memory. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: A data processor apparatus comprises a plurality of processor elements, a memory having a plurality of parts, and a first switching element associated with the first processor element for switchably coupling the first processor element to its associated memory part for at least one of read and write access.

Abstract: A data processor apparatus comprises a plurality of processor elements, a memory having a plurality of parts, and a first switching element associated with the first processor element for switchably coupling the first processor element to its associated memory part for at least one of read and write access.

Abstract: A switching element for switchably coupling a two-dimensional array of circuit elements comprises an input, an output, means for switchably coupling the input to the output; a first input/output port, a second input/output port, a third input/output port, and a fourth input/output port, each input/output port being switchably coupled to the input, the output, and each other, wherein the first and third input/output ports are spaced apart along a first axis, and the second and fourth input/output ports are spaced apart along a second axis, wherein the second axis traverses the first axis between the first and third input/output ports.

Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of memories, an interface for controlling access to the memories by a device, and an identifier identifying at least a memory location in one memory and a memory location in another memory. The interface is responsive to the identifier to condition the memory locations for receiving data and/or for transferring data therefrom. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of processor units couplable to receive data from the memory, and control means for controlling transmission of data from the control means to each processor unit. The control means for controlling operations of the data processor units is arranged to transmit data intended for each processor unit (i.e. broadcast data) to the memory, and is adapted to control each processor unit to receive the broadcast data from the memory. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: An apparatus and method are provided for producing an assembly comprising a memory, a plurality of data buses and an interface for controlling access to the memory by each data bus. The interface is arranged to control memory access so that the plurality of devices can access different parts of the memory substantially simultaneously. A single interface is used to control memory accesses to different parts or elements of a memory substantially simultaneously so that a plurality of, or multiple memory accesses can be performed at the same time.

Abstract: An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.

Abstract: A data processor apparatus comprises a plurality of data receiving means each for receiving data from a data source; a computational element coupleable to each of said data receiving means for performing an operation on said data; and a controller for controlling the flow of data from each data receiving means to the computational element.

Abstract: A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements.

Abstract: A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements.

Abstract: A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability.