Patents by Inventor Malcolm Ware

Malcolm Ware has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080097656
    Abstract: A method and system and calibration technique for power measurement and management over multiple time frames provides responsive power control while meeting global system power consumption and power dissipation limits. Power output of one or more system power supplies is measured and processed to produce power values over multiple differing time frames. The measurements from the differing time frames are used to determine whether or not system power consumption should be adjusted and then one or more devices is power-managed in response to the determination. The determination may compare a set of maximum and/or minimum thresholds to each of the measurements from the differing time frames. A calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor calibration is made at the common mode voltage of the power supply output.
    Type: Application
    Filed: December 21, 2007
    Publication date: April 24, 2008
    Inventors: Dhruv Desai, Nickolas Gruendler, Carl Morrell, Gary Shippy, Michael Scollard, Michael Steinmetz, Malcolm Ware, Christopher Wood
  • Publication number: 20080072005
    Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
    Type: Application
    Filed: November 21, 2007
    Publication date: March 20, 2008
    Applicant: International Business Machines Corporation
    Inventors: Youseff Abdelilah, Bartholomew Blaner, Gordon Davis, Jeffrey Derby, Joseph Garvey, Malcolm Ware, Hua Ye
  • Publication number: 20080069194
    Abstract: A method for operating plurality of DSL modem transmitters integrated within a circuit card. The method includes each DSL modem transmitter: generating a full power physical frame when the DSL modem transmitter is provided with data to transmit; generating a low power physical frame having a control channel signal component and no data; and selecting between the full power physical frame and the low power physical frame for transmission from the DSL modem transmitter, wherein selection of the low power physical frame for transmission from the DSL modem transmitter is based only on the DSL modem transmitter having no data to transmit. The method further includes limiting aggregate flow of data to the plurality of DSL modem transmitters such that a total power required by the plurality of DSL modem transmitters is held below a predefined target power level.
    Type: Application
    Filed: November 26, 2007
    Publication date: March 20, 2008
    Applicant: International Business Machines Corporation
    Inventors: Gordon DAVIS, Jeffrey Derby, Evangelos Eleftheriou, Sedat Oelcer, Malcolm Ware
  • Publication number: 20080027664
    Abstract: A method for estimating power dissipated by a processor core processing a workload-includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 31, 2008
    Inventors: Pradip Bose, Tejas Karkhanis, Srinivasan Ramani, Malcolm Ware, Ken Vu
  • Publication number: 20080010390
    Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
    Type: Application
    Filed: September 17, 2007
    Publication date: January 10, 2008
    Applicant: International Business Machines Corporation
    Inventors: Youseff Abdelilah, Bartholomew Blaner, Gordon Davis, Jeffrey Derby, Joseph Garvey, Malcolm Ware, Hua Ye
  • Publication number: 20070294558
    Abstract: A method and system and calibration technique for power measurement and management over multiple time frames provides responsive power control while meeting global system power consumption and power dissipation limits. Power output of one or more system power supplies is measured and processed to produce power values over multiple differing time frames. The measurements from the differing time frames are used to determine whether or not system power consumption should be adjusted and then one or more devices is power-managed in response to the determination. The determination may compare a set of maximum and/or minimum thresholds to each of the measurements from the differing time frames. A calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor calibration is made at the common mode voltage of the power supply output.
    Type: Application
    Filed: August 22, 2007
    Publication date: December 20, 2007
    Inventors: Dhruv Desai, Nickolas Gruendler, Carl Morrell, Gary Shippy, Michael Scollard, Michael Steinmetz, Malcolm Ware, Christopher Wood
  • Publication number: 20070124094
    Abstract: A histogram difference method and system for power/performance measurement and management has low data storage requirements while supporting multiple monitoring applications having different update rates. Histogram data for power usage and/or performance mode is collected at a predetermined rate and the histogram data is read out at periodic intervals by the monitoring applications. The monitoring applications subtract the histogram data from previously read histogram data set to determine a interval difference histogram. The minimum and maximum values for the interval are the lowest-valued and highest-valued bin in the interval difference histogram that have a count greater than zero. The average value for the interval is the mean of the interval difference histogram. A conservative bound of the maximum and minimum values for a system can be determined by adding the values of the maximum and minimum values determined for each subsystem in the system.
    Type: Application
    Filed: November 29, 2005
    Publication date: May 31, 2007
    Inventors: Thomas Brey, Charles Lefurgy, Mark Rinaldi, Malcolm Ware
  • Publication number: 20060209898
    Abstract: A codec detects congestion in a packet network and responds via a session control protocol to re-negotiate codec-type and/or parameters with the receiving codec to reduce bit rate for supporting a session. Once the connection and session are established, encoded packets start flowing between the two codecs. A control entity sends and receives network congestion control packets periodically in the session. The congestion control packets provide a “heartbeat” signal to the receiving codec. When the network is not congested, all “heartbeat” packets will be passed through the network. As network congestion increases, routers within the network discard excess packets to prevent network failure. The codecs respond to the missing packets by slowing down the bit rate or proceeding to renegotiate a lower bit rate via the session control protocol. If there are no missing packets, the codecs detect if the session is operating at the highest bit rate, and if not, re-negotiate a higher bit rate.
    Type: Application
    Filed: February 7, 2006
    Publication date: September 21, 2006
    Inventors: Youssef Abdelilah, Gordon Davis, Jeffrey Derby, Dongming Hwang, Clark Jeffries, Malcolm Ware, Hua Ye
  • Patent number: 7096411
    Abstract: A system and method for the resynchronization of a sequential decoder that decodes received signal samples stored within an input buffer is disclosed. The system comprises two auxiliary decoders coupled to the sequential decoder for running a simplified MAP decoding process when the input buffer reaches a threshold saturation level. Control of the respective increments of a read pointer and a write pointer allows one to detect the saturation of the input buffer and to derive a sequence of signal samples to the appropriate auxiliary decoder. The selected auxiliary decoder estimates a resynchronization state for the sequential decoder based on the sequence of signal samples. According to the read and the write pointers value, normal sequential decoding is resumed, otherwise, the second auxiliary decoder is selected. The selected auxiliary decoder estimates a resynchronization state for the sequential decoder based on a new sequence of signal samples.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: August 22, 2006
    Assignee: International Business Machines Corporation
    Inventors: Giovanni Cherubini, Malcolm Ware
  • Publication number: 20060156042
    Abstract: A method and system and calibration technique for power measurement and management over multiple time frames provides responsive power control while meeting global system power consumption and power dissipation limits. Power output of one or more system power supplies is measured and processed to produce power values over multiple differing time frames. The measurements from the differing time frames are used to determine whether or not system power consumption should be adjusted and then one or more devices is power-managed in response to the determination. The determination may compare a set of maximum and/or minimum thresholds to each of the measurements from the differing time frames. A calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor calibration is made at the common mode voltage of the power supply output.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 13, 2006
    Inventors: Dhruv Desai, Nickolas Gruendler, Carl Morrell, Gary Shippy, Michael Scollard, Michael Steinmetz, Malcolm Ware, Christopher Wood
  • Publication number: 20060155415
    Abstract: A data processing system attributes energy consumption to individual program segments or threads includes a processor that executes a first thread during a first portion of a measurement interval and a second thread during a second portion of the interval. An energy monitor measures the total energy during the interval. Energy attribution code attributes a first amount of the total energy to the first thread and a second amount to the second thread based in part on the execution times of the threads. The code may define a range of possible energy values by determining maximum and minimum energy constraints for the threads. The invention may also be extended to a multiprocessor environment and to a simultaneous multithreading (SMT) processor. In addition, the process may be expanded to determine energy consumed by various peripheral units such as hard disk controllers and the like.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 13, 2006
    Inventors: Charles Lefurgy, Malcolm Ware
  • Publication number: 20060080625
    Abstract: A method, system, and apparatus for estimating the power dissipated by a processor core processing a workload, where the method includes analyzing a reference test case to generate a reference workload characteristic. Analyzing an actual workload to generate an actual workload characteristic. Performing a power analysis for the reference test case to establish a reference power dissipation value.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 13, 2006
    Inventors: Pradip Bose, Tejas Karkhanis, Srinivasan Ramani, Malcolm Ware, Ken Vu
  • Publication number: 20060039457
    Abstract: A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flow of data packets to the DSLs.
    Type: Application
    Filed: September 28, 2005
    Publication date: February 23, 2006
    Applicant: International Business Machines Corporation
    Inventors: Gordon Davis, Jeffrey Derby, Evangelos Eleftheriou, Sedat Oelcer, Malcolm Ware
  • Publication number: 20060026493
    Abstract: A system and method for the resynchronization of a sequential decoder that decodes received signal samples stored within an input buffer is disclosed. The system comprises two auxiliary decoders coupled to the sequential decoder for running a simplified MAP decoding process when the input buffer reaches a threshold saturation level. Control of the respective increments of a read pointer and a write pointer allows one to detect the saturation of the input buffer and to derive a sequence of signal samples to the appropriate auxiliary decoder. The selected auxiliary decoder estimates a resynchronization state for the sequential decoder based on the sequence of signal samples. According to the read and the write pointers value, normal sequential decoding is resumed, otherwise, the second auxiliary decoder is selected. The selected auxiliary decoder estimates a resynchronization state for the sequential decoder based on a new sequence of signal samples.
    Type: Application
    Filed: May 2, 2003
    Publication date: February 2, 2006
    Inventors: Giovanni Cherubini, Malcolm Ware
  • Publication number: 20050188129
    Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 25, 2005
    Applicant: International Business Machines Corporation
    Inventors: Youseff Abdelilah, Bartholomew Blaner, Gordon Davis, Jeffrey Derby, Joseph Garvey, Malcolm Ware, Hua Ye
  • Publication number: 20050114606
    Abstract: Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed.
    Type: Application
    Filed: November 21, 2003
    Publication date: May 26, 2005
    Applicant: International Business Machines Corporation
    Inventors: Richard Matick, Jaime Moreno, Malcolm Ware