Patents by Inventor Mali Mahalingam
Mali Mahalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907734Abstract: Approaches, techniques, and mechanisms are disclosed for flexible and dynamic modification of elements within textual content to provide an enhanced interface for development or other activities with respect to those elements. In an embodiment, the elements may be augmented with links by which users may quickly access associated items in development tools or other resources. For example, in an embodiment, the elements may be specific lines or blocks of code mentioned in a stack trace or error message. The elements may be transformed into links that, for instance, open the file containing the mentioned line or block of code, and optionally scroll specifically to the mentioned line or block of code. In an embodiment, the elements are specific passages within web pages that match trigger conditions specified by rules encapsulated in a user-customizable client-side plug-in, extensions, or bookmarklet. Proxy-based or server-based implementations may also be used.Type: GrantFiled: April 24, 2019Date of Patent: February 20, 2024Assignee: salesforce.com, inc.Inventors: Dmytro Kashyn, Sergii Puliaiev, Preethi Mali Mahalingam, Vatsal A. Shah
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Publication number: 20200341777Abstract: Approaches, techniques, and mechanisms are disclosed for flexible and dynamic modification of elements within textual content to provide an enhanced interface for development or other activities with respect to those elements. In an embodiment, the elements may be augmented with links by which users may quickly access associated items in development tools or other resources. For example, in an embodiment, the elements may be specific lines or blocks of code mentioned in a stack trace or error message. The elements may be transformed into links that, for instance, open the file containing the mentioned line or block of code, and optionally scroll specifically to the mentioned line or block of code. In an embodiment, the elements are specific passages within web pages that match trigger conditions specified by rules encapsulated in a user-customizable client-side plug-in, extensions, or bookmarklet. Proxy-based or server-based implementations may also be used.Type: ApplicationFiled: April 24, 2019Publication date: October 29, 2020Inventors: Dmytro Kashyn, Sergii Puliaiev, Preethi Mali Mahalingam, Vatsal A. Shah
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Patent number: 9941210Abstract: An embodiment of a semiconductor die includes a base semiconductor substrate and an electrically conductive through substrate via (TSV) extending between the surfaces of the base semiconductor substrate. The bottom surface of the base semiconductor substrate includes a recessed region proximate to the TSV so that an end of the TSV protrudes from the bottom surface, and so that the TSV sidewall has an exposed portion at the protruding end of the TSV. Back metal, consisting of one or more metallic layers, is deposited on the bottom surface of the base semiconductor substrate and in contact with the TSV. The back metal can include a gold layer, a sintered metallic layer, and/or a plurality of other conductive layers. The die may be attached to a substrate using solder, another sintered metallic layer, or other materials.Type: GrantFiled: December 27, 2016Date of Patent: April 10, 2018Assignee: NXP USA, INC.Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, Mali Mahalingam, Colby Rampley
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Publication number: 20180082915Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.Type: ApplicationFiled: September 19, 2016Publication date: March 22, 2018Applicant: FREESCALE SEMICONDUCTOR INC.Inventors: LAKSHMINARAYAN VISWANATHAN, JAYNAL A. MOLLA, DAVID ABDO, MALI MAHALINGAM, CARL D'ACOSTA
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Patent number: 9922894Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.Type: GrantFiled: September 19, 2016Date of Patent: March 20, 2018Assignee: NXP USA, INC.Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, David Abdo, Mali Mahalingam, Carl D'Acosta
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Publication number: 20090001614Abstract: An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.Type: ApplicationFiled: September 4, 2008Publication date: January 1, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Brian W. Condie, Mali Mahalingam, Mahesh K. Shah
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Patent number: 7435625Abstract: Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ? and/or lower loss tangent ? than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ? buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower ? buffer region reduces the parasitic loss in the encapsulation. Low ? and/or ? buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ? less than about 3.0 and/or ? less than about 0.005.Type: GrantFiled: October 24, 2005Date of Patent: October 14, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Brian W. Condie, Mali Mahalingam, Mahesh K. Shah
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Publication number: 20070090542Abstract: Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ? and/or lower loss tangent ? than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ? buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower ? buffer region reduces the parasitic loss in the encapsulation. Low ? and/or ? buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ? less than about 3.0 and/or ? less than about 0.005.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Mali Mahalingam, Mahesh Shah
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Patent number: 7091602Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).Type: GrantFiled: December 13, 2002Date of Patent: August 15, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Alexander J. Elliott, L. Mali Mahalingam, William M. Strom