Patents by Inventor Malitha KULATUNGA

Malitha KULATUNGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • State table complexity reduction in a hierarchical verification flow
    Patent number: 11222154
    Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 11, 2022
    Assignee: Synopsys, Inc.
    Inventors: Kaushik De, Rajarshi Mukherjee, David L. Allen, Bhaskar Pal, Sanjay Gulati, Gaurav Pratap, Nishant Patel, Malitha Kulatunga, Sachin Bansal
  • STATE TABLE COMPLEXITY REDUCTION IN A HIERARCHICAL VERIFICATION FLOW
    Publication number: 20210110093
    Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 15, 2021
    Inventors: Kaushik DE, Rajarshi MUKHERJEE, David L. ALLEN, Bhaskar PAL, Sanjay GULATI, Gaurav PRATAP, Nishant PATEL, Malitha KULATUNGA, Sachin BANSAL