Abstract: Specialized image processing circuitry is usually implemented in hardware in a massively parallel way as single instruction multiple data (SIMD) architectures. Known implementations suffer from the long and complicated connection paths between a processing element and the memory subsystem, and the resulting limitation of maximum operating frequency. An optimized architecture for image processing has processing elements that are arranged in a two-dimensional structure, and each processing element has a local storage containing a plurality of reference pixels that are not neighbors in the reference image. Instead, the reference pixels belong to different blocks of the reference image, which may vary for different encoding schemes.

Abstract: So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ messages to be sent back to the transmitter in an SCH packet in a QOS mode (Quality Of Service), in which all the LCH data packets must be confirmed by the receiver. Space for the LCH and SCH data packets must be provided in a buffer store in the Hiperlan/2 interface for each connection that is set up. When there is a possibility of several hundred connections having been set up, separate reservation of memory areas for LCH and SCH packets would involve considerable complexity for the memory organization. The invention proposes that only one common area be reserved for LCH and SCH packets in the buffer store. The section which is provided for each LCH package is of such a size that it corresponds to a value 2n where n?[0, 1, 2, 3, . . .

Abstract: During the transmission of data packets received on a wired connection via a first interface (e.g. IEEE 1394 interface) via a second interface designed for the wireless transmission of data, e.g. HIPERLAN/2 interface, the problem exists that between receiving the data and transmitting the data via the second interface a relatively large delay time can arise which must be bridged by means of a suitably dimensioned buffer memory. The invention provides means that enable the maximum delay time to be further reduced. For this purpose, according to the invention, the necessary processing of the received IEEE 1394 bus packets is already performed section by section immediately after a received data packet has arrived. After the complete number of bus packets falling within a transmission frame has been received, there is therefore no longer any lengthy processing time required and the probability of missing the time slots reserved in the next transmission frame is significantly reduced.

Abstract: So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ messages to be sent back to the transmitter in an SCH packet in a QOS mode (Quality Of Service), in which all the LCH data packets must be confirmed by the receiver. Space for the LCH and SCH data packets must be provided in a buffer store in the Hiperlan/2 interface for each connection that is set up. When there is a possibility of several hundred connections having been set up, separate reservation of memory areas for LCH and SCH packets would involve considerable complexity for the memory organization. The invention proposes that only one common area be reserved for LCH and SCH packets in the buffer store. The section which is provided for each LCH package is of such a size that it corresponds to a value 2n where n&egr;[0, 1, 2, 3, . . .

Abstract: The invention deals with a wireless extension of the IEEE 1394 bus. Considered is a scenario where two clusters of 1394 devices are linked to each other by means of a wireless bridge (9). The devices of one cluster shall communicate with devices of the other cluster without being bridge-aware. The wireless bridge, however, provides for a bus reset isolation. This causes a problem each time a bus reset occurs in one of the clusters. To solve this problem it is proposed to implement a buffer memory (22) for self-identification packets in the 1394 interfaces (11) of both boxes of said wireless bridge (9). In particular these buffer memories (22) shall be implemented in the physical layer section (21) of the 1394 interfaces (11).