Abstract: A light source assembly includes a plurality of cells and a driving circuit. Each of the cells includes a transistor and a light source. The transistor includes a drain region that serves as a cathode of the light source. The driving circuit is configured to drive the cell. An optical sensor cell and a method for manufacturing thereof are also disclosed.

Abstract: A light-emitting diode (LED) assembly comprises a plurality of LED cells and a driving circuit. Each of the LED cells includes an LED and a transistor. The LED includes first and second LED layers and an LED electrode. The first LED layer includes a III-V compound semiconductor. The second LED layer is over the first LED layer. The LED electrode is over the second LED layer. The first LED layer is free of an LED electrode. The transistor includes a drain region connected to the first LED layer. The driving circuit is configured to drive the LED cells.

Abstract: A light-emitting diode (LED) assembly comprises a plurality of LED cells and a driving circuit. Each of the LED cells includes an LED and a transistor. The LED includes first and second LED layers and an LED electrode. The first LED layer includes a III-V compound semiconductor. The second LED layer is over the first LED layer. The LED electrode is over the second LED layer. The first LED layer is free of an LED electrode. The transistor includes a drain region connected to the first LED layer. The driving circuit is configured to drive the LED cells.

Abstract: A light source assembly includes a plurality of cells and a driving circuit. Each of the cells includes a transistor and a light source. The transistor includes a drain region that serves as a cathode of the light source. The driving circuit is configured to drive the cell. An optical sensor cell and a method for manufacturing thereof are also disclosed.

Abstract: A new structure and method with a process tracking current source component to program a flash EPROM memory is proposed. By applying a current source which varies not only with the process variation but also with the source bias of the cell being programmed, a self-convergent and high-efficiency programming can be achieved. This process tracking current source component provides less current for cells with higher erased Vt and larger current for cells with lower erased Vt. A circuit for programming a floating gate transistor includes a current source component. The current source component couples in series between the floating gate transistor and an electrical sink during a programming interval. The current source component includes an electrical characteristic substantially matching the electrical characteristic of the floating gate transistor. An integrated circuit memory module on a semiconductor substrate is disclosed.

Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

Abstract: A new structure and method with a process tracking current source component to program a flash EPROM memory is proposed. By applying a current source which varies not only with the process variation but also with the source bias of the cell being programmed, a self-convergent and high-efficiency programming can be achieved. This process tracking current source component provides less current for cells with higher erased Vt and larger current for cells with lower erased Vt.

Abstract: An ESD protection structure for protecting an internal circuit comprising a primary protection device, a secondary protection device, and a substrate pickup is presented. The primary protection device and secondary protection device share a common source, and this common source implementation lowers the trigger voltage of the primary protection device to be about the same as the trigger voltage of the secondary protection device, thereby eliminating the need to use an isolation resistor between the primary and secondary protection devices.

Abstract: The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.

Abstract: The present invention provides a method of performing optical proximity corrections of a photo mask pattern by using a computer. The photo mask pattern is formed on a photo mask which is used when performing photolithography for forming a predetermined original pattern by exposing a photo-resist layer in a predetermined area of a semiconductor wafer. The photo mask pattern is divided into a plurality of rectangular blocks. Each block can be bright or dark, and a least one side and two corners of the block are shared with another block. Each of shared corners is checked to find corners which may be affected by an optic proximity effect, and those corners are modified so as to prevent them from being affected by the optic proximity effect.

Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

Abstract: Mask ROMS with fixed code implantation and associated integrated circuits are described. An integrated circuit has a Mask ROM including: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cell by a set of select lines, and the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column. The use of fixed code implantation results in a single current path during the reading of a given memory cell and permits the size of the corresponding device to be reduced and have better topography.

Abstract: A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and suicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

Abstract: A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell.

Abstract: The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.

Abstract: A method for programming a semiconductor memory device, such as an EPROM or a Flash EPROM, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. The programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. A wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period. Each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.

Abstract: In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.

Abstract: An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate. Circuitry, coupled to the selected floating gate storage transistor, maintains drain current of the selected floating gate transistor at a substantially stable value during programming. In one example, the circuitry is a stable current source in parallel with a load coupled to the source of the selected floating gate transistor. The stable current source, in one embodiment, is a current mirror designed to supply a fixed current level. The load may be a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.

Abstract: The present invention provides a method of writing a set of binary codes into a ROM. The method is performed by forming a first photo mask and a second photo mask according to an original first code pattern, an original second code pattern, and a set of binary codes to be written into the ROM. Final first and second code patterns are formed by coupling the binary codes to be written with the original first and second code patterns by using a Boolean logical OR operation. The first and second photo masks are formed according to the final first and second code patterns. The first photolithographic process is performed using the first photo mask, and the first ion implantation process is performed; the second photolithographic process is performed using the second photo mask, and the second ion implantation process is performed. Thus the set of binary codes is written into the ROM completely and correctly.

Abstract: A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to a standard cell layout and is adaptable for a variety of output driving specifications according to the need of a particular implementation. A doped region having a first conductivity type is formed in the substrate. A plurality of sets of cascode connected transistors having channels in the doped region is included.