Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Abstract: A method for quality and reliability assurance testing a lot of fabricated ICs comprising the steps of testing the differential Iddq of a sample of ICs at a plurality of different voltages, burning-in a sample of ICs, and then testing the functionality of the sample of ICs. The method of the present invention enables the reliability of an entire lot of ICs to be tested by determining an effective screening voltage for differential Iddq testing of the ICs, thereby eliminating the need both to burn-in and conduct post burn-in testing of all future lots of the ICs. The method of the present invention also enables fabrication facilities and workers to be engaged in other tasks rather than testing of ICs.