Abstract: According to one embodiment, the failure analysis system of the semiconductor device includes a memory, a failure information management table, and an analyzing unit. The memory stores normal/failure information collected in a block unit and a column unit in a chip, in a plurality of inspection processes of the semiconductor memory. The failure information management table stores the normal/failure information in the block unit and the column unit stored in the memory, with an addition of product information, fabricating information including a lot number, a wafer number, and a chip address, process information, and test information, which are common information ranging over the inspection processes. The analyzing unit analyzes the normal/failure information in the block unit and the column unit ranging over the plurality of inspection processes, on the basis of the information stored in the failure information management table.

Abstract: A semiconductor device failure analysis system according to an embodiment of the present invention includes a memory configured to be capable of retaining an initial display information; and a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, the semiconductor device including a three-dimensional memory cell array, and to generate a second image from the first image based on the initial display information, the second image corresponding to part of the plurality of fail bit information. The semiconductor device failure analysis system according to the embodiment further includes a display configured to be capable of initially displaying the second image.

Abstract: A semiconductor device failure analysis system according to an embodiment of the present invention includes a memory configured to be capable of retaining an initial display information; and a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, the semiconductor device including a three-dimensional memory cell array, and to generate a second image from the first image based on the initial display information, the second image corresponding to part of the plurality of fail bit information. The semiconductor device failure analysis system according to the embodiment further includes a display configured to be capable of initially displaying the second image.

Abstract: Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.

Abstract: According to one embodiment, a fail analysis system performs mesh division of a physical fail bit map and stores fail bit map image data of a part bit fail region in a first image data storage region while classifying the fail bit map image data in each contraction ratio, in each chip, and in each layer. The fail analysis system also stores the fail bit map image data in a second image data storage region while classifying the fail bit map image data in each kind of a fail mode, in each contraction ratio, in each chip, and in each layer. Further, based on an instruction of a display format and/or a display region from a user, the fail analysis system extracts the pieces of fail bit map image data from the first image data storage region or second image data storage region to combine the pieces of fail bit map image data, and displays the combined fail bit map image data on a display unit.

Abstract: Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.

Abstract: A defect analysis method for semiconductor memory includes: reading out an address bit map corresponding to an input kind of the memory macro from a database which stores address bit maps respectively corresponding to memory macro kinds; inputting size information of the memory macro; translating a logical address of a defective cell of the memory macro detected on the basis of results of an electric test measured by using a tester to a physical address of a memory macro in a standard disposition by using the input size information and the address bit map read out, of the memory macro, and generating a fail bit map in the standard disposition; inputting disposition information of the memory macro; and translating a physical address of the fail bit map in the standard disposition to a physical address of the memory macro by using the input disposition information of the memory macro, and generating a fail bit map of the memory macro.

Abstract: A scheme for controlling a screen display capable of allowing the addition of new functions such as the note entry and the pointing according to the input events not requested by the application program, and preserving the meaning attributed to the drawings related to the windows even when the window state change is made. The screen display is controlled by transmitting the inputs entered at the input device as input events to an application program, and supplying the display requests made by the application program according to prescribed types of the input events as well as the display requests according to the input events other than the prescribed types to the output device. Also, when the display of the window data is changed, the display of the drawing data is also changed in accordance with a change made in the display of the window data. Drawing data superposes or overlays separate window data.

Abstract: A scheme for supporting cooperative works capable of reproducing the contents of the past works from the recorded history of the cooperative works accurately, such that the cooperative works can be carried out efficiently and smoothly. In this scheme, the inputs made by each user during the cooperative works are stored in correspondence to input target data indicating input target applications of the inputs as a record of the cooperative works. Then, afterwards, the input target applications indicated by the input target data are re-executed according to the stored inputs to reproduce results of the cooperative works resulting from the inputs which can be presented to each user.

Abstract: A scheme for controlling a screen display capable of allowing the addition of new functions such as the note entry and pointing according to the input events not requested by the application program, and preserving the meaning attributed to the drawings related to the windows even when the window state change is made. The screen display is controlled by transmitting the inputs entered at the input device as input events to an application program, and supplying the display requests made by the application program according to the prescribed types of the input events as well as the display requests according to the input events other than the prescribed types to the output device. Input events are transmitted to a window server program and then transmitted to a communication relay program which handles input events and output requests from the application program to the window server.