Abstract: A data transfer circuit according to the invention includes a memory configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit configured to output, as an adjustment multiple ?N, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit generates the second clock by multiplying the reference clock by a rational number (N+?N).

Abstract: A data transfer circuit (40) according to the invention includes a memory (41) configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit (44) configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit (42) configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit (43) configured to output, as an adjustment multiple ?N, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit (44) generates the second clock by multiplying the reference clock by a rational number (N+?N) using the adjustment multiple ?N output from the adjustment circuit (43).