Abstract: A semiconductor device includes an alignment mark. A probe beam is scanned on the alignment mark so as to detect a position coordinate of the alignment mark, and the alignment mark comprises a plurality of bar marks which are arranged in a first predetermined interval along a first direction of scanning the detection beam. Each of the plurality of bar marks comprises a plurality of interconnection marks which are arranged along a second direction orthogonal to the first direction, and a first space between adjacent two of the plurality of interconnection marks is shorter than a wavelength of the detection beam within a range of a design constraint.

Abstract: A semiconductor device includes a semiconductor substrate, and an insulating layer that is provided on the semiconductor substrate, wherein, in an internal circuit formation region of the insulating layer, a via hole and an interconnect trench, that is formed on the via hole and communicates with the via hole, are provided, in the via hole and the interconnect trench, a conductor is provided so as to integrally fill the via hole and said interconnect trench, in a dicing region of the insulating layer, a groove portion and an opening, that communicates with the groove portion and is formed to cover the groove portion when the semiconductor substrate is seen in plane view, are formed, and in the groove portion and the opening, a conductor is provided so as to integrally fill the groove portion and the opening.

Abstract: A semiconductor device includes a semiconductor substrate, and an insulating layer that is provided on the semiconductor substrate, wherein, in an internal circuit formation region of the insulating layer, a via hole and an interconnect trench that is formed on the via hole and communicates with the via hole are provided, in the via hole and the interconnect trench, a conductor is provided so as to integrally bury the via hole and said interconnect trench, in a dicing region of the insulating layer, a groove portion and an opening that communicates with the groove portion and is formed to cover the groove portion when the semiconductor substrate is seen in plane view from the side of the substrate surface are formed, and in the groove portion and the opening, a conductor is provided so as to integrally bury the groove portion and the opening.

Abstract: A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.

Abstract: A semiconductor device includes an alignment mark. A probe beam is scanned on the alignment mark so as to detect a position coordinate of the alignment mark, and the alignment mark comprises a plurality of bar marks which are arranged in a first predetermined interval along a first direction of scanning the detection beam. Each of the plurality of bar marks comprises a plurality of interconnection marks which are arranged along a second direction orthogonal to the first direction, and a first space between adjacent two of the plurality of interconnection marks is shorter than a wavelength of the detection beam within a range of a design constraint.

Abstract: A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.

Abstract: An electron beam exposure mask comprises a main mask and one or more compensation masks. The main mask has a plurality of first defined masks. The compensation mask includes one or more non-defective second defined masks each having a pattern configuration to be formed in a defective among said first defined masks. In performing exposures by using this electron beam exposure mask, first defined masks are used as long as the first defined masks are non-defective, and the second defined mask corresponding to a first defined mask is used when the first defined mask is defective.

Abstract: An electron beam exposure mask comprises a main mask and one or more compensation masks. The main mask has a plurality of first defined masks. The compensation mask includes one or more non-defective second defined masks each having a pattern configuration to be formed in a defective among said first defined masks. In performing exposures by using this electron beam exposure mask, first defined masks are used as long as the first defined masks are non-defective, and the second defined mask corresponding to a first defined mask is used when the first defined mask is defective.

Abstract: An electron beam exposure mask comprises a main mask and one or more compensation masks. The main mask has a plurality of first defined masks. The compensation mask includes one or more non-defective second defined masks each having a pattern configuration to be formed in a defective among said first defined masks. In performing exposures by using this electron beam exposure mask, first defined masks are used as long as the first defined masks are non-defective, and the second defined mask corresponding to a first defined mask is used when the first defined mask is defective.

Abstract: An electron beam exposure mask comprises a main mask and one or more compensation masks. The main mask has a plurality of first defined masks. The compensation mask includes one or more non-defective second defined masks each having a pattern configuration to be formed in a defective among said first defined masks. In performing exposures by using this electron beam exposure mask, first defined masks are used as long as the first defined masks are non-defective, and the second defined mask corresponding to a first defined mask is used when the first defined mask is defective.

Abstract: An electron beam exposure mask comprises a main mask and one or more compensation masks. The main mask has a plurality of first defined masks. The compensation mask includes one or more non-defective second defined masks each having a pattern configuration to be formed in a defective among said first defined masks. In performing exposures by using this electron beam exposure mask, first defined masks are used as long as the first defined masks are non-defective, and the second defined mask corresponding to a first defined mask is used when the first defined mask is defective.

Abstract: A mask for electron beam exposure used in a process for exposing a wafer with predetermined patterns for a chip by an EB projection lithography system. The mask comprises: a grillage area; a plurality of thin film areas surrounded by the grillage area and having a thickness thinner than that of the grillage area; and a plurality of mask pattern areas each of which is formed within respective one of the thin film areas. Each of the mask pattern areas has mask patterns corresponding to patterns of a subfield obtained by dividing the patterns for a chip into a plurality of areas having substantially the same shape and size. The wafer is exposed with predetermined patterns for a chip by performing, for each of the mask pattern areas, a step of irradiating an electron beam onto the mask for electron beam exposure such that the center of an area irradiated by the electron beam coincides with the center of each of the mask pattern areas.