Patents by Inventor Mami Nakadate
Mami Nakadate has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200154602Abstract: A tank includes: a first housing configured to include a first inner surface and a first peripheral edge projecting from the first inner surface; a second housing configured to include a second inner surface and a second peripheral edge, the second inner surface facing the first inner surface, the second peripheral edge projecting from the second inner surface and facing the first peripheral edge; and a sticky elastic body inside the first and second peripheral edge, wherein the first peripheral edge has a first inclined surface inclined from inside to outside from the first inner surface toward a first projecting end of the first peripheral edge, the second peripheral edge has a second inclined surface inclined from inside to outside from the second inner surface toward a second projecting end of the second peripheral edge, and the elastic body is stuck to the first and second inclined surface.Type: ApplicationFiled: October 14, 2019Publication date: May 14, 2020Applicant: FUJITSU LIMITEDInventors: Shingo YAMAGUCHI, Satoshi Kanbayashi, Hayato Shida, MAMI NAKADATE, Kanako IMAI, Yukari Sato
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Publication number: 20190212248Abstract: A non-transitory computer-readable recording medium storing a distortion calculation program that causes a computer to execute a process includes: analyzing a distortion which occurs in an object when stress is applied, referring to a storage which stores a distortion amplitude for each of nodes of a mesh which is created for the object, moving, onto a circumference which is determined by a set radius, one or more nodes within a width set from the circumference by using a point selected from the nodes of the mesh as a starting point, creating a distribution chart of values of the distortion amplitude of the one or more nodes on the circumference after movement, and displaying the distribution chart on a display device.Type: ApplicationFiled: January 4, 2019Publication date: July 11, 2019Applicant: FUJITSU LIMITEDInventors: MAMI NAKADATE, Kanako IMAI, Yukari Sato
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Patent number: 9317648Abstract: A board design aid device includes a calculating and correcting units. The calculating unit groups a plurality of layers in a multi-layer board into a plurality of pairs of layers based on design information of the multi-layer board, the plurality of layers being stacked and derives a difference of total amounts in respect to a board design element, each of the total amounts being related to each layer of a pair of layers of the plurality of pairs of layers, the board design element being related to a warp of the multi-layer board. The correcting units, based on the difference of the total amounts, corrects an amount of the board design element for at least one of layers among at least one of the plurality of the pairs of layers so that the difference of the total amounts of the board design element is maintained within a certain range.Type: GrantFiled: April 8, 2014Date of Patent: April 19, 2016Assignee: FUJITSU LIMITEDInventors: Mami Nakadate, Tetsuyuki Kubota, Shigeo Ishikawa
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Publication number: 20140310677Abstract: A board design aid device includes a calculating and correcting units. The calculating unit groups a plurality of layers in a multi-layer board into a plurality of pairs of layers based on design information of the multi-layer board, the plurality of layers being stacked and derives a difference of total amounts in respect to a board design element, each of the total amounts being related to each layer of a pair of layers of the plurality of pairs of layers, the board design element being related to a warp of the multi-layer board. The correcting units, based on the difference of the total amounts, corrects an amount of the board design element for at least one of layers among at least one of the plurality of the pairs of layers so that the difference of the total amounts of the board design element is maintained within a certain range.Type: ApplicationFiled: April 8, 2014Publication date: October 16, 2014Applicant: FUJITSU LIMITEDInventors: Mami NAKADATE, Tetsuyuki Kubota, Shigeo ISHIKAWA
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Patent number: 8744810Abstract: A bonding surface extraction unit extracts, with reference to bonding information, data of a first bonding surface corresponding to a bottom surface of a bonding model from data of a first partial model and data of a second bonding surface corresponding to a top surface of the bonding model from data of a second partial model. The first partial model is a model of a pad included in a circuit board. The second partial model is a model of an electrode included in a component. The electrode is to be bonded to the pad with a bonding material. A bonding model generation unit generates a side surface establishing a link between outlines of the first bonding surface and the second bonding surface, and obtains data of the bonding model on the basis of a shape formed with the side surface, the first bonding surface, and the second bonding surface.Type: GrantFiled: February 9, 2011Date of Patent: June 3, 2014Assignee: Fujitsu LimitedInventors: Nobutaka Itoh, Makoto Sakairi, Mami Nakadate, Yoshiteru Ochi, Akiyoshi Saitou
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Patent number: 8482291Abstract: A substrate includes a first plate member; a plurality of first electrodes provided on the major surface of the first plate member, the first electrodes including at least one electrode for circuit connection and at least one monitor electrode separate from the electrode for circuit connection; a second plate member; a plurality of second electrodes provided on the major surface of the second plate member; a plurality of solder members provided between the first electrodes and the second electrodes for electrical connection therebetween, repeatedly; and a detector for detecting an electrical disconnection between at least one of the monitor electrode and the second electrode.Type: GrantFiled: April 28, 2010Date of Patent: July 9, 2013Assignee: Fujitsu LimitedInventors: Nobutaka Itoh, Makoto Sakairi, Mami Nakadate
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Publication number: 20110208485Abstract: A bonding surface extraction unit extracts, with reference to bonding information, data of a first bonding surface corresponding to a bottom surface of a bonding model from data of a first partial model and data of a second bonding surface corresponding to a top surface of the bonding model from data of a second partial model. The first partial model is a model of a pad included in a circuit board. The second partial model is a model of an electrode included in a component. The electrode is to be bonded to the pad with a bonding material. A bonding model generation unit generates a side surface establishing a link between outlines of the first bonding surface and the second bonding surface, and obtains data of the bonding model on the basis of a shape formed with the side surface, the first bonding surface, and the second bonding surface.Type: ApplicationFiled: February 9, 2011Publication date: August 25, 2011Applicant: FUJITSU LIMITEDInventors: Nobutaka ITOH, Makoto Sakairi, Mami Nakadate, Yoshiteru Ochi, Akiyoshi Saitou
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Publication number: 20100289500Abstract: A substrate includes a first plate member; a plurality of first electrodes provided on the major surface of the first plate member, the first electrodes including at least one electrode for circuit connection and at least one monitor electrode separate from the electrode for circuit connection; a second plate member; a plurality of second electrodes provided on the major surface of the second plate member; a plurality of solder members provided between the first electrodes and the second electrodes for electrical connection therebetween, repeatedly; and a detector for detecting an electrical disconnection between at least one of the monitor electrode and the second electrode.Type: ApplicationFiled: April 28, 2010Publication date: November 18, 2010Applicant: FUJITSU LIMITEDInventors: Nobutaka Itoh, Makoto Sakairi, Mami Nakadate
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Patent number: 7730444Abstract: A structural analysis method that saves analysis time without lowering the prediction accuracy is provided. The structural analysis method has dividing up the analysis target into a plurality of finite elements; defining a plurality of meshes that divide up the analysis target into units larger than the finite elements and calculating, for each mesh, the proportion of one material among the plurality of materials that occupy the finite element contained in the mesh; specifying a mesh in which the calculated proportion of the one material exceeds a predetermined threshold value and generating mesh data by substituting material information specifying materials other than the one material with material information of the materials of the finite elements contained in the specified mesh; and calculating the physical amount yielded in the analysis target on the basis of the generated mesh data.Type: GrantFiled: October 27, 2005Date of Patent: June 1, 2010Assignee: Fujitsu LimitedInventors: Nobutaka Itoh, Tetsuyuki Kubota, Mami Nakadate, Akira Tamura
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Patent number: 7596477Abstract: The present invention provides a peel strength simulating apparatus which simulates peel strength between a semiconductor integrated circuit chip and a resin package bonded to each other. The apparatus includes a storage section which stores plural types of parameters. The apparatus also includes a parameter specifying section which specifies a changeable parameter whose numerical value is changeable from the plural types of parameters stored in the storage section and specifies change priorities when specifying plural types of changeable parameters. The apparatus further includes a simulating section which repeats simulation of the peel strength until the peel strength exceeding a predetermined threshold value is obtained while changing the numerical values of the specified changeable parameters according to the specified priorities.Type: GrantFiled: March 8, 2006Date of Patent: September 29, 2009Assignee: Fujitsu LimitedInventor: Mami Nakadate
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Patent number: 7502714Abstract: The present invention relates to optimization analysis achieving a target value and provides a device, method and program ensuring improved analysis efficiency and analysis accuracy. The device includes an analysis unit (CPU 14), an evaluation unit (CPU 14) and a condition modification unit (CPU 14). The analysis unit executes an analysis with analysis conditions imparted thereto. The evaluation unit evaluates the analysis results. The condition modification unit modifies the analysis conditions imparted to the analysis unit, based on the evaluation results. An optimum solution is thus derived by performing one or more analyses through the modification of the given analysis conditions.Type: GrantFiled: December 22, 2004Date of Patent: March 10, 2009Assignee: Fujitsu LimitedInventors: Mami Nakadate, Nobutaka Itoh
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Publication number: 20070138652Abstract: The present invention provides a peel strength simulating apparatus which simulates peel strength between a semiconductor integrated circuit chip and a resin package bonded to each other. The apparatus includes a storage section which stores plural types of parameters. The apparatus also includes a parameter specifying section which specifies a changeable parameter whose numerical value is changeable from the plural types of parameters stored in the storage section and specifies change priorities when specifying plural types of changeable parameters. The apparatus further includes a simulating section which repeats simulation of the peel strength until the peel strength exceeding a predetermined threshold value is obtained while changing the numerical values of the specified changeable parameters according to the specified priorities.Type: ApplicationFiled: March 8, 2006Publication date: June 21, 2007Applicant: FUJITSU LIMITEDInventor: Mami Nakadate
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Publication number: 20070061030Abstract: In order to analyze the reliability of a package, firstly, a manufacturing process analysis simulating unit conducts and analyzes a manufacturing process analysis simulation. Then, a reliability evaluation analysis simulating unit conducts and analyzes reliability evaluation analysis simulation. Each simulation analysis result is reflected in a manufacturing process one after another and manufactures a package. A shipping determination unit final determines whether the manufactured package can be shipped. Thus, an optimal package can be selected by multiplying the reliability analysis which takes into consideration the history of heat given to a package in its manufacturing process, of a material (resin) and a structure (package dimensions) suitable for designed thermal load conditions. Simultaneously, the number and cost of its trial manufacture can be reduced. A package structure which matches the material characteristic of a package can be determined by feedback.Type: ApplicationFiled: December 22, 2005Publication date: March 15, 2007Applicant: Fujitsu LimitedInventors: Mami NAKADATE, Nobutaka ITOH
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Publication number: 20060173660Abstract: A structural analysis method that saves analysis time without lowering the prediction accuracy is provided. The structural analysis method has dividing up the analysis target into a plurality of finite elements; defining a plurality of meshes that divide up the analysis target into units larger than the finite elements and calculating, for each mesh, the proportion of one material among the plurality of materials that occupy the finite element contained in the mesh; specifying a mesh in which the calculated proportion of the one material exceeds a predetermined threshold value and generating mesh data by substituting material information specifying materials other than the one material with material information of the materials of the finite elements contained in the specified mesh; and calculating the physical amount yielded in the analysis target on the basis of the generated mesh data.Type: ApplicationFiled: October 27, 2005Publication date: August 3, 2006Applicant: FUJITSU LIMITEDInventors: Nobutaka Itoh, Tetsuyuki Kubota, Mami Nakadate, Akira Tamura
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Publication number: 20060052984Abstract: The present invention relates to optimization analysis achieving a target value and provides a device, method and program ensuring improved analysis efficiency and analysis accuracy. The device includes an analysis unit (CPU 14), an evaluation unit (CPU 14) and a condition modification unit (CPU 14). The analysis unit executes an analysis with analysis conditions imparted thereto. The evaluation unit evaluates the analysis results. The condition modification unit modifies the analysis conditions imparted to the analysis unit, based on the evaluation results. An optimum solution is thus derived by performing one or more analyses through the modification of the given analysis conditions.Type: ApplicationFiled: December 22, 2004Publication date: March 9, 2006Applicant: FUJITSU LIMITEDInventors: Mami Nakadate, Nobutaka Itoh
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Publication number: 20050234687Abstract: In a technique for dividing an object, which is to be analyzed numerically and is made up of a plurality of components, into grids to generate fundamental elements, grid setting according to the situation becomes possible, and the time required for grid division or analysis can be shortened while securing sufficient precision of analysis. This invention involves a setting step of, in a data converting process, setting an allowable range of an aspect ratio of fundamental elements for numerical analysis to each of the components, a cube dividing step of, in the data converting process, dividing each of the components into a plurality of cubes within the aspect ratio allowable range to generate a cube division model, and a grid dividing step of dividing each of the components into grids according to the cube division model to generate fundamental elements for numerical analysis.Type: ApplicationFiled: May 24, 2005Publication date: October 20, 2005Applicant: Fujitsu LimitedInventors: Makoto Sakairi, Mami Nakadate
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Publication number: 20040158450Abstract: The present invention relates to a solder joint life prediction method for predicting the joint life of joining solder which joins members with each other. It predicts the life of soldered joints with high accuracy in a short period of time. It observes phase growth in a crack pre-initiation stage, extrapolates the phase growth, and thereby predicts the time of crack initiation when an initial crack will appear in the joining solder. After the crack initiation, the present invention predicts the time of fracture using a simulation in which creep analysis is performed with a virtual initial crack given to data-based joining solder.Type: ApplicationFiled: February 3, 2004Publication date: August 12, 2004Applicant: FUJITSU LIMITEDInventors: Mami Nakadate, Makoto Sakairi