Abstract: A data slice circuit which generates a EFM signal from a RF signal includes a clock signal generator circuit for generating a clock signal not synchronized with the EFM signal. The data slice circuit divides a clock signal not synchronized with the EFM signal, by a divider, to generate a clock signal for counting. The clock signal for counting is inputted as a clock into an up/down counter. Up/down count control of the up/down counter is performed on the basis of an output from a comparator. The comparator compares the RF signal with a reference voltage and outputs data "1" or "0" in accordance with the comparison result. A count output of the up/down counter is converted into an analog voltage by a digital/analog converter and is supplied as a reference voltage to the comparator.

Abstract: In a disc reproducing apparatus using a VCO (voltage controlled oscillator) circuit, the VCO circuit includes a first delay cell array having gates supplied with a first control voltage DCV, a ring oscillator including a second delay cell array having gates supplied with a second control voltage Vin, and a switch for selecting the number of delay cells from the second delay cell array. The oscillation frequency of the ring oscillator is determined by a time delay of the second delay cell array. When the second control voltage Vin having the same value as the first control voltage DCV is inputted to the gates of the delay cells of the second delay cell array, the ring oscillator oscillates with a frequency determined by the ratio of the number of the delay cells of the first delay cell array to number of the delay cells of the second delay cell array.