Abstract: A message system for logically synchronizing a large number of tester chips includes a message pipeline for multiple sets of tester chips. Each set of tester chips includes a delay unit through which messages are communicated to the message pipeline from the set of tester chips and from the message pipeline to the set of tester chips, and a message accumulation unit for temporarily holding the messages communicated from the message pipeline to the set of tester chips. The message pipeline runs at a first clock rate that is governed by a first clock source and the messages are communicated to the set of tester chips from the message accumulation unit at a second clock rate that is governed by a second clock source that is different from the first clock source.