Abstract: A vehicle control device includes a remaining capacity detecting module that detects a remaining capacity of a secondary battery which supplies an electric power to the drive motor, and a cruise mode switching module that switches a cruise mode from the first cruise mode to the second cruise mode on the basis of the remaining capacity, and switches the cruise mode from the second cruise mode to the first cruise mode on the basis of an external charging.

Abstract: A vehicle control device includes a remaining capacity detecting module that detects a remaining capacity of a secondary battery which supplies an electric power to the drive motor, and a cruise mode switching module that switches a cruise mode from the first cruise mode to the second cruise mode on the basis of the remaining capacity, and switches the cruise mode from the second cruise mode to the first cruise mode on the basis of an external charging.

Abstract: A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

Abstract: The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words, and transferring the main code words to one of a plurality of memory banks. The semiconductor device also includes a data output portion for receiving one page worth of data, including main code words transferred from the data latch circuit, correcting errors in the data when the data includes fewer than a predetermined number of errors for each main code word, adding the error information to each read code word, and outputting the result.

Abstract: A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

Abstract: A data recording and/or playing method for recording or playing data to or from an optical disc having a first recording area, where a frame sync signal and the data are recorded, and a second recording area, where a predetermined pattern is preformed, and having address data recorded therein, while rotating the optical disc by a rotation drive unit. The optical disc rotated by the rotation drive unit is scanned by a head unit, and when the head unit is scanning the first recording area, the rotation drive unit is controlled in a first rotation control mode. When the head unit is scanning the second recording area, the rotation drive unit is controlled in a second rotation control mode.

Abstract: A disk recording apparatus for recording data to a disk includes: a reading and writing element for emitting a read beam onto the disk to read out recorded data therefrom while emitting a plurality of write beams simultaneously onto the disk to record data thereto in parallel; and a controlling element for controlling where to emit on the disk the plurality of write beams in accordance with the data read out by the reading and writing element.

Abstract: A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data), for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

Abstract: The present invention provides a data recording and/or playing method for recording or playing data to or from an optical disc (1 or 11) having a first recording area (3, 12b or 13b) where a frame sync signal and the data are recorded, and a second recording area (5 or 14) where a predetermined pattern is preformed, and having address data recorded therein, while rotating the optical disc (1 or 11) by means of a rotation drive unit (56 or 62). The optical disc rotated by the rotation drive unit (56 or 62) is scanned by a head unit (55 or 63). When the head unit (55 or 63) is scanning the first recording area (3, 12b or 13b), the rotation drive unit (56 or 62) is controlled in a first rotation control mode. When the head unit (55 or 63) is scanning the second recording area (5 or 14), the rotation drive unit (56 or 62) is controlled in a second rotation control mode.

Abstract: An information detecting circuit for detecting whether copyright protecting information inserted in recording data is illegal or not is provided. The information detecting circuit is provided so as to detect recording data modulated by a predetermined modulating circuit. When the information detecting circuit determines that the copyright protecting information is illegal, at least the illegal copyright protecting information is prevented from being recorded on a recording medium as it is. With such a configuration, when the detecting operation of the information detecting circuit is performed on a hardware level, the possibility of illegal data copying by altering software, for example, can be eliminated completely.

Abstract: A disk recording apparatus for recording data to a disk is disclosed. The apparatus includes: a reading and writing element for emitting a read beam onto the disk to read out recorded data therefrom while emitting a plurality of write beams simultaneously onto the disk to record data thereto in parallel; and a controlling element for controlling where to emit on the disk the plurality of write beams in accordance with the data read out by the reading and writing element.

Abstract: An apparatus of forming an evaluation signal used in adjusting focus bias and adjusting skew of a disk drive in which phase error information between a phase of a read data signal and a phase of a clock signal formed in synchronism with the read data signal, is detected, the phase error signal is converted into an analog signal and is outputted as an evaluation signal having a signal level in accordance with the phase error amount and the evaluation signal is inputted after A/D conversion to a portion for carrying out signal quality evaluation by using the evaluation signal whereby pertinent signal evaluation can be carried out by a simple constitution.

Abstract: An apparatus of forming an evaluation signal used in adjusting focus bias and adjusting skew of a disk drive in which phase error information between a phase of a read data signal and a phase of a clock signal formed in synchronism with the read data signal, is detected, the phase error signal is converted into an analog signal and is outputted as an evaluation signal having a signal level in accordance with the phase error amount and the evaluation signal is inputted after A/D conversion to a portion for carrying out signal quality evaluation by using the evaluation signal whereby pertinent signal evaluation can be carried out by a simple constitution.

Abstract: A servo control system for a shock-proof disk player comprising a digital signal processor, a voltage-controlled oscillator, a reference clock generator, a clock mode changeover switch, a phase comparator for controlling a head-rotating spindle motor, and a bulk memory of a large capacity for storage of data, wherein the phase lock of a PLL at the time of a seek is switched on or off under control to thereby shorten the required seek time. The clock signal frequency is selectively changed in such a manner as to lock the PLL in accordance with the rotation rate, whereby the power consumption can be lowered. The bulk memory is used as a data buffer, and the servo system is controlled as the data are read out from the memory while the data quantity stored and left therein is detected, so that a reduction of the power consumption can be achieved with another advantage of enhancing the resistance against shock.

Abstract: In a disk recording/reproduction apparatus, the operational limit of each of a mechanical apparatus and signal processing of a disk drive is taken into consideration. When an area from the innermost region of a disk to a predetermined distance is recorded or reproduced, the disk is rotationally driven by a CAV method, and when an area from the predetermined distance of the disk to the outermost region is recorded or reproduced, the disk is rotationally driven by a CLV method.

Abstract: A disc reproduction apparatus, configured so that a voltage-controlled oscillator is used as a means of giving a reference frequency to an analog phase-locked loop circuit, a control voltage based on a speed error of the rotational speed of a spindle with respect to the reference speed is given to this voltage-controlled oscillator by a rotational speed counting circuit, and a reference clock is produced in the analog phase-locked loop circuit based on the oscillation frequency given by this voltage-controlled oscillator and, at the same time, the reproduction clock PLLCK is produced by the digital phase-locked loop circuit based on this reference clock, whereby the operation becomes stable with respect to rotational outer disturbances and high speed access is enabled.

Abstract: A disc reproduction apparatus, configured so that a voltage-controlled oscillator is used as a device of giving a reference frequency to an analog phase-locked loop circuit, a control voltage based on a speed error of the rotational speed of a spindle with respect to the reference speed is given to this voltage-controlled oscillator by a rotational speed counting circuit, and a reference clock is produced in the analog phase-locked loop circuit based on the oscillation frequency given by this voltage-controlled oscillator and, at the same time, the reproduction clock PLLCK is produced by the digital phase-locked loop circuit based on this reference clock, whereby the operation becomes stable with respect to rotational outer disturbances and high speed access is enabled.

Abstract: A plurality of pickups are provided for reading information recorded on a disc. Each of the pickups is provided with a signal processing system and a control system. Each of the signal processing systems and control systems is controlled by a system controller such that, while one pickup is reading the information, another pickup is moved to a next information reading position and put in a standby state. As soon as the former pickup has completed the reading operation, the latter pickup gets out of standby state to be ready for reading the information at the above-mentioned position. The novel setup reduces seek time significantly.

Abstract: Provision is made of a traverse cycle measuring circuit for measuring the traverse cycle based on a signal CNIN obtained by digitalizing the tracking error signal at the time of a track traverse, a register in which any target value of the traverse cycle can be set, a circuit for comparing the measured traverse cycle and set target value, control circuits, for controlling the tracking and sled so that the detected speed of traverse converges to a target value, and counting circuits for counting the number of traversed tracks based on the signal CNIN, the target value of the register being reset to a value by which the speed of traverse is reduced when the count of the counting circuit reaches a number of tracks (N-.alpha.) smaller than the target number of tracks by exactly .alpha..

Abstract: An error correction method comprises the steps of loading a value stored in a syndrome register (15) to syndrome registers (16) to (18) if error is a single-error after syndrome registers [S0 to S3] (15) to (18) had finished calculating syndromes and loading values stored in the syndrome registers (16) to (18) to data registers [R1 to R3] (22) to (24), repeating multiplications of powers of .alpha., .alpha..sup.2, .alpha..sup.3 by using the syndrome registers (15) to (18) until coincidence detecting circuits (25) to (28) detect that the values of the syndrome registers (15) to (18) and the values of the data registers (22) to (24) are agreed, energizing a counter (29) in synchronism with the multiplications of powers, setting a count value obtained when it is detected that the values of the syndrome registers and the values of the data registers are agreed to a data location and effecting error correction based on the value of the syndrome register [S0] (15) used as an error amount.