Abstract: A semiconductor memory of the present invention includes a plurality of memory cell regions each being constituted by a particular memory cell and a plurality of word lines for selecting the memory cells. A word line driver circuit activates one word line to which a memory cell designated by the address signal is connected. A bit line connected to the memory cell selected by the activated word line reads data out of the memory cell. A sense amplifier amplifies a potential difference between two adjoining bit lines forming a bit line pair. A sense amplifier precharge circuit charges a power supply line and a ground line, which feed a voltage to the sense amplifier, to a preselected voltage. A driver circuit feeds to the gates of a first and a second n-channel MOS transistors in the sense amplifier precharge circuit a control signal of a preselected high level voltage from a third n-channel MOS transistor.

Abstract: A semiconductor memory device having redundant memory selection circuit XRDN which outputs a redundant replacement selection signal for each bank. In a refreshing operation, each redundant decoder XRED only compares an address indicated by row address signal XADD with an address of a defective memory cell stored, without referring to a bank selection signal included in row address signal XADD. Redundant memory cell selection circuit XRDN outputs redundant replacement selection signals XRDNS(A), (B) for respective banks A, B, for indicating a bank in which the replacement is to be performed with a redundant memory cell.

Abstract: The present invention provides a synchronous memory device having at least a multi-bit pre-fetch address generator circuit, and at least an access path which includes at least a command decoder having an output terminal connected to at least a follower circuit element which receives a command signal from the at least a command decoder, wherein the at least a multi-bit pre-fetch address generator circuit is connected to the at least a follower circuit element in parallel to the at least a command decoder, so that the at least a multi-bit pre-fetch address generator circuit is excluded from a transmission path of the command signal, whereby the at least a multi-bit pre-fetch address generator circuit generates a plurality of internal address signals independently from transmission of the command signal from the at least a command decoder to the at least a follower circuit element.

Abstract: A semiconductor memory device is provided that includes a plurality of normal memory cells, a device for activating the memory cells in response to an externally applied address and a plurality of redundant memory cells. A memory and comparison device may include a device for storing an address of a failed memory cell existing within a plurality of normal memory cells and a device for comparing the externally applied address with the failed memory cell address. A redundant memory cell selection device may select any one of a plurality of redundant memory cells in response to an output signal output from the memory and comparison device. A redundant memory cell activating device may activate the redundant memory cell, responsive to an output of the memory and comparison device.

Abstract: A semiconductor memory device comprising a plurality of memory cell arrays including a redundant memory cell for each. Connection between each memory cell array and data input-output terminals can be switched easily by a signal input from the outside in response to a plurality of input-output data widths. Each redundant memory cell compares each bit of an external address input externally with each bit of an internal address of a memory cell having been stored. According to a detection signal from a redundancy judging circuit to detect agreement between both addresses, the memory cell having that address is replaced. This replacement can be carried out not only within the memory cell array having the redundant memory cell but also between different memory cell arrays.

Abstract: External control signals are input to a semiconductor memory device via a synchronizing semiconductor circuit. An internal clock (ICLK) in the synchronizing semiconductor circuit is produced as a phase shifted version of an external clock (S11) which is input to the memory device. First latch circuits (321-324) latch external control signals in response to the external clock (S11). Decoder circuits (331.sub.0 -331.sub.n) produce internal control signals (S31.sub.0 -S331.sub.n) based upon the latched signals (S21-S24) output from the first latch circuits (321-324). Second latch circuits (341.sub.0 -341.sub.n) latch the internal control signals (S31.sub.0 14 S31.sub.n) in response to the internal clock signal (ICLK).

Abstract: A semiconductor memory device has an input circuit for inputting reference clocks, an input buffer circuit for latching external input signals in synchronization with the reference clocks, and an output buffer circuit for outputting a stored data to an outside in synchronization with the reference clocks. The input buffer circuit and the output buffer circuit are caused to operate at respectively different edges of the reference clocks for processing one and the same stored data. The device may include an internal read-out circuit system which reads-out the stored data in accordance with the external input signal and which is caused to operate solely based on an edge at which the input buffer circuit operates. Between the internal read-out system and the output buffer circuit, there is provided a buffer circuit which temporarily stores the stored data read-out by the internal read-out circuit system until the stored data is outputted by the output buffer.

Abstract: The synthetic resin at a projecting end portion (5) projected from a clamping device (9) is heated to melt, then the projecting end portion (5) is positioned in a press molding space, which comprises an opening between an aluminum foil layer (3c) of a laminated aluminum tube and a molding wall of the press molding space. The projecting end portion (5) is pressed and molded into a sealed portion in the press molding space. The tube produced with this method has a sealed portion (8) with a desired shape, the aluminum foil layer (3) at the sealed portion (8) being completely covered and encapsulated with the synthetic resin, and the density of the sealed portion (8) improves providing excellent sealing quality.

Abstract: To obtain high access speed regardless of a structure and operating characteristics of an external central processing unit (CPU), a synchronous dynamic random access memory (DRAM) system includes first and second DRAM cell arrays, and a first address generator for outputting a first address and a second address respectively to the first and second DRAM cell arrays simultaneously in a first mode. In a second mode, the first address generator outputs the first address and the second address respectively to the first and second DRAM cell arrays sequentially.

Abstract: A coating apparatus comprises a coating vessel holding a coating liquid with a liquid leakage preventing member having an opening. A cylindrical member such as a cylindrical support for supporting a photosensitive member is inserted into the opening and the cylindrical member is moved relative to the coating liquid vessel in the vertical direction. A scraping member for scraping the coating liquid is at least partially immersed in the coating liquid, or is positioned above the surface of the coating liquid in the coating liquid vessel, the scraping member being almost concentric to the cylindrical member and movable in the radial direction of the cylindrical member. The cylindrical member is axially aligned with the scraping member using coating liquid pressure applied to the scraping member to coincide the center of the scraping member with the center of the cylindrical member.

Abstract: A semiconductor memory device has an input circuit for inputting reference clocks, an input buffer circuit for latching external input signals in synchronization with the reference clocks, and an output buffer circuit for outputting a stored data to an outside in synchronization with the reference clocks. The input buffer circuit and the output buffer circuit are caused to operate at respectively different edges of the reference clocks for processing one and the same stored data. The device may include an internal read-out circuit system which reads-out the stored data in accordance with the external input signal and which is caused to operate solely based on an edge at which the input buffer circuit operates. Between the internal read-out system and the output buffer circuit, there is provided a buffer circuit which temporarily stores the stored data read-out by the internal read-out circuit system until the stored data is outputted by the output buffer.

Abstract: A synchronous semiconductor memory with a burst transfer mode is comprised of a plurality of memory cell subarrays. A plurality of internal data buses operates with an input buffer circuit to transfer data in parallel to the subarrays. The input buffer includes a shift register composed of a first and second cascade connected registers. A register output selector distributes the data signals in parallel to the plurality of internal buses.

Abstract: In the semiconductor memory of this invention, a first unit of data that is inputted by means of the same standard clock as an external address and that is inputted to a chip prior to determination of the internal address signal that is prefetched is latched to all latch circuits into which this data may be latched. After an address is determined by the next standard clock, second and succeeding units of data inputted to the chip are inputted only to latch circuits that are latched in accordance with address signals. In this way, even if internal address signal processing has not been completed at the time of latching the first unit of data, both the first unit of data and second and succeeding units of data can be latched in prefetch circuits designated by addresses from the outside.

Abstract: In a semiconductor memory, the output of a ROM (Read Only Memory) storing the address of replacement with a redundant cell is compared with the leading address of a burst input to the memory from the outside. A signal representative of the coincidence the leading address and the replaced address is attained without waiting for the generation of internal addresses, so that a rapid access to a redundant cell array is achievable. The replacement to the redundant cell is effected collectively on a burst length basis. Alternatively, the replacement may be effected by activating the cell array with the coincidence signal, then comparing the internal addresses generated later with the replaced address in the burst, and then switching the input and output portion of each array.

Abstract: A redundancy decoder circuit includes an output line U which takes an active level when an access address supplied thereto is coincident with a redundant address programmed therein. This circuit further includes a fuse F which is blown to deactivate the decoder or not blown to activate the decoder, a latch circuit latching a level responsive to a blown or not-blown state of the fuse, and a transistor controlled by the latch circuit to forcibly hold the output line at an inactive level when the fuse is blown.

Abstract: An apparatus and method for forming a seal portion of a tubular body of synthetic resin is provided in which the seal portion has increased density and reduced foaming. The apparatus includes a pair of clamps that clamp an end portion of a tubular body of resin flat. A heater heats and fuses a projecting end portion projecting from the clamps. A bending member bends side projecting portions of the body formed during heating so that they are inwardly projecting. A press member presses the projecting end portion to form a seal portion.

Abstract: A production process with good efficiency, and applicable to production of a synthetic intermediate of a new quinolone anti-fungus agent CP-99219, is provided.A production process of an intermediate of a new quinolone compound expressed by the formula (IV) ##STR1## wherein R.sup.3 represents a benzyl group, a diphenylmethyl group, etc. and R.sup.4 represents a linear or branched alkyl group of 1 to 8C, a cycloalkyl group, etc.which process employs as a starting substance, a cyclopropanetricarboxylic acid triester expressed by the formula (I) ##STR2## wherein R.sup.1 and R.sup.2 represent a linear or branched alkyl group, a cycloalkyl group, an aryl group or an aralkyl group,and passes through seven steps.

Abstract: A dynamic random access memory device of a dual word line structure is disclosed, which comprises a plurality of memory array blocks, each of the memory array blocks including at least one main-word line, a plurality of sub-word lines, a plurality of sub-word drivers having an input node connected to the main-word line, an output node connected to an associated one of the sub-word lines and a power node, each of the sub-word drivers responding to an active level of the main-word line to drive the associated sub-word line with a power voltage supplied to the power node, and a decoding unit for, when activated, supplying the power voltage to the power nodes of the sub-word line drivers, and the decoding unit of one of the memory array blocks being activated in response to address information.

Abstract: A dynamic random access memory device selects a row of memory cells from a plurality of memory cell sub-arrays with main word lines and sub-word lines for a data access, and data bits read out from the row of memory cells are amplified by a sense amplifier circuit array, wherein a row block address decoder and a column block address decoder supply a first enable signal and a second enable signal to a row of memory cell sub-arrays and a column of memory cell sub-arrays so that only one of the sense amplifier circuit arrays is powered for the amplification, thereby decreasing peak current consumed by the sense amplifier circuit arrays.

Abstract: A semiconductor memory device, wherein memory cell arrays MA11, 12, 13, . . . are arranged in a matrix. First driving circuits Da11, 12, 13, . . . and second driving circuits Db11, 12, 13, . . . are arranged alternately at the intersections of the word driver WD11, 12, 13, . . . columns and the sensing circuit SC11, 12, 13 . . . rows. The first driving circuits Da11, 12, 13, . . . serve to drive the sense amplifiers SA11, 12, 13, . . . of the sensing circuits SC11, 12, 13, . . . , and the second driving circuits Db11, 12, 13, . . . to drive the precharge circuits PC11, 12, 13, . . . and transfer circuits TG11, 12, 13, . . . so that a sensing circuit SC11, 12, 13, . . . is driven by the first and second driving circuits Da11, 12, 13, . . . and Db11, 12, 13, . . . on opposite sides of it.