Patents by Inventor Mamoru Iizuka

Mamoru Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9240106
    Abstract: Disclosed is an automatic transaction apparatus comprising an upper unit and a lower unit, wherein a means is provided for reducing the cost of manufacturing the upper unit. An automatic transaction apparatus comprises: an upper unit (2a) provided with a bill deposit/withdrawal part (3) and a sorting part (4); and a lower unit (2b) comprising denomination-specific cassettes (13) and a reject storage part (15). The automatic transaction apparatus is provided with: an upper conveyance path (7) which conveys bills to the parts in the upper unit (2a); and a lower conveyance path (10) which is connected to the upper conveyance path (7) and is disposed in the lower unit (2b), and which branches midway and conveys bills to the denomination-specific cassettes (13) or the reject storage part (15).
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: January 19, 2016
    Assignee: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Mamoru Iizuka
  • Publication number: 20130153361
    Abstract: Disclosed is an automatic transaction apparatus comprising an upper unit and a lower unit, wherein a means is provided for reducing the cost of manufacturing the upper unit. An automatic transaction apparatus comprises: an upper unit (2a) provided with a bill deposit/withdrawal part (3) and a sorting part (4); and a lower unit (2b) comprising denomination-specific cassettes (13) and a reject storage part (15). The automatic transaction apparatus is provided with: an upper conveyance path (7) which conveys bills to the parts in the upper unit (2a); and a lower conveyance path (10) which is connected to the upper conveyance path (7) and is disposed in the lower unit (2b), and which branches midway and conveys bills to the denomination-specific cassettes (13) or the reject storage part (15).
    Type: Application
    Filed: May 9, 2011
    Publication date: June 20, 2013
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Mamoru Iizuka
  • Patent number: 6441484
    Abstract: A semiconductor device comprises: a first semiconductor chip having a control circuit; a plurality of second semiconductor chips whose operation is controlled by the control circuit; and a resin sealing body for sealing the first semiconductor chip and the plurality of second semiconductor chips, wherein: the first semiconductor chip is arranged in the central portion of the resin sealing body; and the plurality of second semiconductor chips are arranged on a periphery of the first semiconductor chip. A fuse element is further arranged outside the plurality of second semiconductor chips.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: August 27, 2002
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Kenji Koyama, Norinaga Arai, Akio Mikami, Mamoru Iizuka
  • Publication number: 20010048148
    Abstract: A semiconductor device comprises: a first semiconductor chip having a control circuit; a plurality of second semiconductor chips whose operation is controlled by the control circuit; and a resin sealing body for sealing the first semiconductor chip and the plurality of second semiconductor chips, wherein: the first semiconductor chip is arranged in the central portion of the resin sealing body; and the plurality of second semiconductor chips are arranged on a periphery of the first semiconductor chip. A fuse element is further arranged outside the plurality of second semiconductor chips.
    Type: Application
    Filed: May 18, 2001
    Publication date: December 6, 2001
    Inventors: Kenji Koyama, Norinaga Arai, Akio Mikami, Mamoru Iizuka