Patents by Inventor Mamoru Ishida

Mamoru Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180047940
    Abstract: An organic EL display device including a TFT substrate (substrate) and an organic EL element (electroluminescent element) that is provided on the TFT substrate includes a sealing layer that seals the organic EL element. The sealing layer is composed of a laminated structure that is constituted by an organic film and first and second inorganic films. Recessed/protruding portions are provided on surfaces of the organic film and the first and second inorganic films.
    Type: Application
    Filed: February 25, 2016
    Publication date: February 15, 2018
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tohru SONODA, Takeshi HIRASE, Tetsuya OKAMOTO, Tohru SENOO, Daichi NISHIKAWA, Mamoru ISHIDA
  • Publication number: 20180040848
    Abstract: An organic EL display device (electroluminescence device) including a TFT substrate (substrate), an organic EL element (electroluminescence element) disposed on the TFT substrate, a first inorganic film covering the organic EL element, at least one protruding body having a frame shape, the at least one protruding body being configured by an organic film and surrounding the electroluminescence element on the first inorganic film, a second inorganic film covering the first inorganic film and the at least one protruding body, and a leveled film configured by an organic film and provided on the second inorganic film.
    Type: Application
    Filed: February 9, 2016
    Publication date: February 8, 2018
    Inventors: Takeshi HIRASE, Tetsuya OKAMOTO, Tohru SENOO, Tohru SONODA, Mamoru ISHIDA
  • Publication number: 20180040849
    Abstract: An organic EL display 1 includes a sealing film 2 provided on a plastic substrate 10 to cover an organic EL element 4. The sealing film 2 includes a first sealing layer 25 on a surface of the plastic substrate 10, three stress relief layers 26, 27, and 28 on a surface of the first sealing layer 25, and a second sealing layer 29 on a surface of the stress relief layer 28. The stress relief layers 26, 27, and 28 each have a higher coefficient of thermal expansion than the first and second sealing layers 25 and 29. The stress relief layer 27 interposed between the stress relief layers 26 and 28 has a higher coefficient of thermal expansion than the stress relief layers 26 and 28.
    Type: Application
    Filed: February 12, 2016
    Publication date: February 8, 2018
    Inventors: MAMORU ISHIDA, TETSUYA OKAMOTO, TAKESHI HIRASE, TOHRU SENOO, TOHRU SONODA, DAICHI NISHIKAWA
  • Publication number: 20180010244
    Abstract: A mask comprises a mask substrate having a protruding section in an opening end surface of an opening, having an acute angle defined by ?1 and ?2 of no more than 43°, and having a height from a film-formation surface on the substrate to a tip section of the protruding section greater than the thickness of the film to be formed on the film-formation surface.
    Type: Application
    Filed: January 22, 2016
    Publication date: January 11, 2018
    Inventors: TETSUYA OKAMOTO, TAKESHI HIRASE, TOHRU SENOO, TOHRU SONODA, DAICHI NISHIKAWA, MAMORU ISHIDA
  • Publication number: 20170365815
    Abstract: A the organic EL display 1 includes: a first substrate 10; an organic EL element 4 provided above the first substrate 10; and a multilayer sealing film 2 provided above the first substrate 10 to cover the organic EL element 4, and including a barrier layer and a buffer layer lower in hardness than the barrier layer. The organic EL element covered with the multilayer sealing film includes a protrusion, and a relationship (d/h)<2 holds where h is a height of the protrusion directly below the buffer layer and d is a thickness of the buffer layer.
    Type: Application
    Filed: November 30, 2015
    Publication date: December 21, 2017
    Inventors: TOHRU SONODA, TAKESHI HIRASE, TETSUYA OKAMOTO, TOHRU SENOO, DAICHI NISHIKAWA, MAMORU ISHIDA
  • Publication number: 20170338442
    Abstract: An organic EL display device 1 includes a flexible plastic substrate 10, an organic EL element 4 on the plastic substrate 10, and to sealing film 2 provided on the plastic substrate 10 to cover the organic EL element 4. The sealing film 2 includes a first sealing layer 25 on a surface of the plastic substrate 10, a stress relief layer 26 on a surface of the first sealing layer 25, and a second sealing layer 27 on a surface of the stress relief layer 26. Compressive stress of the first sealing layer 25 is lower than compressive stress of the second sealing layer 27.
    Type: Application
    Filed: December 4, 2015
    Publication date: November 23, 2017
    Inventors: MAMORU ISHIDA, KAZUHIKO TSUDA, YOSHIFUMI OHTA
  • Publication number: 20170324061
    Abstract: An organic EL display device 1 that includes a TFT substrate (substrate) 2 and an organic EL element (electroluminescent element) 4 provided on the TFT substrate 2 includes a sealing film 14 that seals the organic EL element 4. The sealing film 14 has a layered structure composed of an organic layer 14b and inorganic layers 14a, 14c. At least a peripheral portion 14b2 of the organic layer 14b has a lower carbon content than a central portion 14b1 of the organic layer 14b.
    Type: Application
    Filed: October 8, 2015
    Publication date: November 9, 2017
    Inventors: Tohru SONODA, Takeshi HIRASE, Tetsuya OKAMOTO, Tohru SENOO, Seiji FUJIWARA, Daichi NISHIKAWA, Mamoru ISHIDA
  • Publication number: 20170263892
    Abstract: In an organic EL display device (electroluminescence device) including a flexible TFT substrate (substrate), an organic EL element (electroluminescence element) provided on the TFT substrate, and a sealing film that seals the organic EL element, a foldable bend portion is provided. The film thickness of the sealing film is reduced at the bend portion.
    Type: Application
    Filed: September 17, 2015
    Publication date: September 14, 2017
    Inventors: Tohru SENOO, Takeshi HIRASE, Tetsuya OKAMOTO, Tohru SONODA, Mamoru ISHIDA, Seiji FUJIWARA, Daichi NISHIKAWA
  • Publication number: 20150256164
    Abstract: According to one embodiment, a timing measuring circuit is provided with N (N is an integer of 2 or more) delay circuits and a comparison circuit. The N delay circuits delay a reference signal by different delay times. The comparison circuit outputs N timing adjustment values based on results of comparison between the reference signal and N output signals from the delay circuits.
    Type: Application
    Filed: September 3, 2014
    Publication date: September 10, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasushi EBATO, Nariyuki FUKUDA, Kazuhito HOSAKA, Isao OOIGAWA, Takeshi YAMAGUCHI, Mamoru ISHIDA, Eiji BAN, Kazumi HAYASHIDA
  • Publication number: 20070034304
    Abstract: A metal-made high-precision gear and a gear mechanism are disclosed. The precision gear is made of a novel material which does not exist in conventional materials for precision gears, including resins and tool steels, has high hardness, strength and excellent surface smoothness, and is superior in workability. In the precision gear which is formed of an amorphous metal alloy having a ternary, quaternary or higher composition containing iron group elements, such as Fe, Co, Ni, and Cu, Ti, Zr, Hf, as the principal elements, the precision gear whose module is 0.2 or less is made of the amorphous metal alloy having a disordered structure which does not have a fixed regularity and whose XRD pattern is a halo pattern, namely exhibits a broad peak.
    Type: Application
    Filed: September 1, 2004
    Publication date: February 15, 2007
    Inventors: Akihisa Inoue, Yukiharu Shimizu, Kazuhiko Kita, Daichi Watanabe, Mamoru Ishida, Hideki Takeda, Yasunori Saotome
  • Publication number: 20060254747
    Abstract: An apparatus provided is capable of performing injection molding of a high-melting point metal. The injection molding apparatus comprises a mold, a sleeve disposed so as to be movable forward and backward toward a pouring gate of the mold, a plunger slidably disposed in the sleeve, a heating means for heating and melting a raw material lump supplied into a raw material accommodating part formed by an inside wall of the sleeve and the plunger mentioned above, and a raw material lump supplying means for supplying the raw material lump to the above-mentioned raw material accommodating part from above. For the purpose of ensuring that a melt of a metal which has been heated and melted hardly flows into a gap between the plunger and the sleeve, the above-mentioned plunger and/or sleeve is equipped with a cooling means.
    Type: Application
    Filed: July 14, 2006
    Publication date: November 16, 2006
    Inventors: Mamoru Ishida, Makoto Kawanishi
  • Patent number: 6758602
    Abstract: An optical connector comprises a mount having an accommodating portion and an optical connector ferrule. The mount and the outer surface of the optical connector ferrule to be brought into contact therewith are made of the same kind of material, thereby securing the good weldability therebetween. In one embodiment, both the mount and the ferrule are made of an amorphous alloy. In another embodiment, the mount is made of a metal, for example stainless steel, and the ferrule comprises a body made of an amorphous alloy and a surface part covering the outer surface of the body is made of the same kind of material as the mount, i.e. a metal such as stainless steel.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: July 6, 2004
    Assignee: YKK Corporation
    Inventors: Tadashi Yamaguchi, Tetsuya Katsumi, Mamoru Ishida, Hitoshi Ofune
  • Publication number: 20030002817
    Abstract: An optical connector comprises a mount having an accommodating portion and an optical connector ferrule. The mount and the outer surface of the optical connector ferrule to be brought into contact therewith are made of the same kind of material, thereby securing the good weldability therebetween. In one embodiment, both the mount and the ferrule are made of an amorphous alloy. In another embodiment, the mount is made of a metal, for example stainless steel, and the ferrule comprises a body made of an amorphous alloy and a surface part covering the outer surface of the body is made of the same kind of material as the mount, i.e. a metal such as stainless steel.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 2, 2003
    Applicant: YKK Corporation
    Inventors: Tadashi Yamaguchi, Tetsuya Katsumi, Mamoru Ishida, Hitoshi Ofune
  • Patent number: 6435731
    Abstract: An optical connector ferrule has an optical fiber incorporated therein as an integral part thereof, wherein the optical fiber is integrally fixed in the ferrule directly or through the medium of the metal tube embedded in the ferrule. This ferrule of the optical fiber built-in type can be produced by inserting an optical fiber or a metal tube having an optical fiber fitted therein into a mold provided with a molding cavity which defines the outer shape of an optical connector ferrule, injecting a fluid material kept at an elevated temperature into the cavity of the mold, and solidifying the cast material by cooling. The optical fiber or both the optical fiber and the metal tube are strongly fixed in the ferrule integrally by the thermal shrinkage or coagulation shrinkage of the ferrule during the production thereof.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: August 20, 2002
    Assignees: YKK Corporation, NTT Advanced Technology Corporation
    Inventors: Tadashi Yamaguchi, Tetsuya Katsumi, Mamoru Ishida
  • Patent number: 5847466
    Abstract: A semiconductor device having a multilayer interconnection structure, includes a substrate having a metal interconnect layer provided thereon and N number (N being an integer of 2 or greater) of layers of insulating film formed one on top of another on the substrate. Each layer of insulating film has a metal interconnect layer including at least one bonding pad section provided thereon. At least one via hole filled with an electrically conductive material is provided in each of the layers for interconnecting metal interconnect layers. At least one bonding pad connecting hole filled with an electrically conductive material is provided in each of the layers for interconnecting bonding pad sections. The at least one bonding pad connecting hole is no more than twice as large in diameter as a smallest via hole.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: December 8, 1998
    Assignee: Ricoh Company, Ltd.
    Inventors: Kazunori Ito, Mitsugu Irinoda, Kaichi Ueno, Mamoru Ishida, Takahiko Kuroda
  • Patent number: 5395874
    Abstract: A flame retardant resin composition which includes 100 weight parts of a rubber-reinforced styrene-based resin, 2.about.35 weight parts of an epoxy-oligomer of tetrabromobisphenol-A (A1), 2.about.35 weight parts of bis-(tribromophenoxy)ethane (A2), 1.about.15 weight parts of antimony trioxide (B), and 0.1.about.10 weight parts of chlorinated polyethylene (C), wherein the total of the above (A1), (A2), (B) and (C) are 8.about.50 weight parts and the weight ratio of (A1)/(A2) is 10/90.about.75/25. The composition of the present invention has well-balanced flame retardance and impact resistance.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: March 7, 1995
    Assignee: Kanegafuchi Kagaku Kogyo Kabushiki Kaisha
    Inventors: Ikuhiro Mishima, Rika Munakata, Mamoru Ishida
  • Patent number: 5365109
    Abstract: A MIS semiconductor device comprises, on a silicon wafer, a gate oxide layer, a polysilicon gate electrode comprising a gate layer of polysilicon of grain size of not less than 0.3 .mu.m doped with boron in a doping amount of not less than 3.times.10.sup.19 atoms/cm.sup.3, and a gate insulation layer, provided with metal electrodes.
    Type: Grant
    Filed: August 11, 1992
    Date of Patent: November 15, 1994
    Assignee: Ricoh Company, Ltd.
    Inventor: Mamoru Ishida
  • Patent number: 4883766
    Abstract: A method of producing a thin film transistor comprises the steps of preparing a structure having a substrate, an active layer and a diffusion layer formed on the substrate, and a gate electrode formed on the active layer, forming on the structure an interlayer insulator layer made of a silicon oxide hydrate (SiO.sub.x H.sub.y) having a predetermined composition, forming contact holes in the interlayer insulator layer, forming a wiring layer on the interlayer insulator layer, and carrying out a thermal process thereby diffusing hydrogen atoms within the interlayer insulator layer into at least the active layer and the diffusion layer.
    Type: Grant
    Filed: November 10, 1988
    Date of Patent: November 28, 1989
    Assignees: Ricoh Company, Ltd., Ricoh Research Institute of General Electronics
    Inventors: Mamoru Ishida, Shunichi Inaki, Yoshikazu Akiyama, Mitsuhiro Kohata