Patents by Inventor Mamoru Kajihara

Mamoru Kajihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5656833
    Abstract: A gate array type semiconductor device has a plurality of basic array block cells. The basic array block cells are made up of at least one basic cell and only one input/output cell. Additionally, the basic array block cells are arranged in a matrix form on a mother wafer. The number of the basic cells in each basic array block cell is determined by a gate scale requirement but the number of input/output cells remain one. Different pellet sizes may be provided on the same mother wafer. This enables to produce various kinds of gate arrays in a short turn around time and a low cost.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: August 12, 1997
    Assignee: NEC Corporation
    Inventor: Mamoru Kajihara
  • Patent number: 5616957
    Abstract: A semiconductor chip 1 is fixedly adhered to an island 2 of a lead frame with a die bonding material 4. The electrode pad positioned at an upper surface of the semiconductor chip 1 and a lead 3 of the lead frame are interconnected with a bonding wire 5. To the semiconductor chip 1, a heat spreader 6 is adhered with an insulating adhesive agent 7. The semiconductor chip 1, the island 2, an inner lead portion 3a of lead 3, the bonding wire 5 and the heat spreader 6 are sealed with sealing resin 8. Since, after completion of the die bonding and wire bonding processes, the heat spreader 6 is adhered to the chip 1, a high temperature die bonding and a high temperature wire bonding become possible without taking the thermal characteristics of the adhesive agent into account.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: April 1, 1997
    Assignee: NEC Corporation
    Inventor: Mamoru Kajihara