Patents by Inventor Mamoru Mita

Mamoru Mita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150093516
    Abstract: A metal-film forming method of the present invention includes a surface activation process of irradiating a laser beam to the surface of the base metal, thereby activating the surface of the basemetal, a noble-metal nanoparticle dispersion liquid coating process of coating the surface of the base metal with a noble-metal nanoparticle dispersion liquid, a solvent thereof, containing noble-metal nanoparticles in as-dispersed state, and a noble-metal nanoparticle sintering process of irradiating the laser beam to the noble-metal nanoparticle dispersion liquid coated on the surface of the base metal, thereby causing the noble-metal nanoparticles to be sintered. Further, a scudding press process of executing press forming of a base metal, and the metal-film forming process of applying noble-metal plating to the surface of the base metal are executed on the same line.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 2, 2015
    Inventors: Shinji ARAGA, Nobuyuki MIYAGI, Mitsugu YAMAGUCHI, Kentaro NAKATA, Mamoru MITA, Katsuhiro MAEKAWA, Kazuhiko YAMASAKI
  • Patent number: 8230591
    Abstract: An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: July 31, 2012
    Assignees: Hitachi Cable, Ltd., Renesas Electronics Corporation
    Inventors: Akira Chinda, Nobuaki Miyamoto, Koki Hirasawa, Kenji Uchida, Mamoru Mita
  • Patent number: 8101864
    Abstract: An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: January 24, 2012
    Assignees: Hitachi Cable, Ltd., Renesas Electronics Corporation
    Inventors: Akira Chinda, Nobuaki Miyamoto, Koki Hirasawa, Kenji Uchida, Mamoru Mita
  • Patent number: 7888697
    Abstract: A lead frame includes a base material, a reflection layer formed on a part of the base material, and a characteristic sustaining layer formed at least on the reflection layer to cover the reflection layer for sustaining a characteristic of the reflection layer by isolating the reflection layer from an outside. The reflection layer includes the characteristic to exhibit a predetermined reflectivity to light with a predetermined wavelength, and the characteristic sustaining layer prevents a decrease in the reflectivity of the reflection layer and transmits light reflected by the reflection layer.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 15, 2011
    Assignees: Hitachi Cable Precision Co., Ltd.
    Inventors: Tadashi Kawanobe, Yuichi Ohnuma, Mamoru Mita
  • Patent number: 7780836
    Abstract: On both surfaces of an electric insulating material 1, a surface conductive layer 2A and a back surface conductive layer 2B are formed by transcription. Further, a via hole 5 penetrating through the surface conductive layer 2A and the electric insulating material 1 is provided. After forming a photosensitive plating resist pattern 14, the via hole 5 is filled with a copper plating filler 15, and the surface wiring layer 9A and the back surface wiring layer 9B are formed. Thereafter, the photosensitive plating resist pattern 14 as well as the surface conductive layer 2A and the back surface conductive layer 2B provided under the photosensitive plating resist pattern 14 are removed to fabricate a double-sided wiring board 11.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: August 24, 2010
    Assignees: Hitachi Cable, Ltd.
    Inventors: Akira Chinda, Nobuaki Miyamoto, Mamoru Mita
  • Publication number: 20090211796
    Abstract: An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 27, 2009
    Inventors: Akira Chinda, Nobuaki Miyamoto, Koki Hirasawa, Kenji Uchida, Mamoru Mita
  • Publication number: 20090141498
    Abstract: A lead frame includes a base material, a reflection layer formed on a part of the base material, and a characteristic sustaining layer formed at least on the reflection layer to cover the reflection layer for sustaining a characteristic of the reflection layer by isolating the reflection layer from an outside. The reflection layer includes the characteristic to exhibit a predetermined reflectivity to light with a predetermined wavelength, and the characteristic sustaining layer prevents a decrease in the reflectivity of the reflection layer and transmits light reflected by the reflection layer.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 4, 2009
    Inventors: Tadashi KAWANOBE, Yuichi Ohnuma, Mamoru Mita
  • Publication number: 20080201943
    Abstract: An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.
    Type: Application
    Filed: April 17, 2008
    Publication date: August 28, 2008
    Inventors: Akira Chinda, Nobuaki Miyamoto, Koki Hirasawa, Kenji Uchida, Mamoru Mita
  • Patent number: 7268408
    Abstract: A wiring board which can realize a small and thin passive component such as solid condenser, resistor, coil, transistor or so on is provided. A wiring board which forms an electronic component by mounting a passive element, comprising an insulating board provided with an opening having predetermined pattern, a wiring formed with predetermined pattern on said insulating board, and an external terminal filled to said opening, connected with said wiring by said filling, and exposed to a bottom of said insulating board where said wiring is formed.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: September 11, 2007
    Assignee: Hitachi Cable Ltd.
    Inventors: Akira Chinda, Akira Matsuura, Takayuki Yoshiwa, Mamoru Mita, Takashi Kageyama, Katsutoshi Taga
  • Patent number: 7202570
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Publication number: 20060225918
    Abstract: An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.
    Type: Application
    Filed: March 16, 2006
    Publication date: October 12, 2006
    Inventors: Akira Chinda, Nobuaki Miyamoto, Koki Hirasawa, Kenji Uchida, Mamoru Mita
  • Patent number: 7038325
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: May 2, 2006
    Assignees: Hitachi Cable, Ltd., Renesas Technology Corp.
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Publication number: 20040224149
    Abstract: The object of the present invention is provide a semiconductor device in semiconductor package configuration, characterized by excellent connection reliability ensured by incorporating a buffer for absorbing differences in thermal expansion rate between a mounting substrate and a semiconductor element even when an organic material is used for a mounting substrate.
    Type: Application
    Filed: December 1, 2003
    Publication date: November 11, 2004
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Publication number: 20040195702
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 7, 2004
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Patent number: 6791194
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Publication number: 20030178713
    Abstract: A wiring board which can realize a small and thin passive component such as solid condenser, resistor, coil, transistor or so on is provided. A wiring board which forms an electronic component by mounting a passive element, comprising an insulating board provided with an opening having predetermined pattern, a wiring formed with predetermined pattern on said insulating board, and an external terminal filled to said opening, connected with said wiring by said filling, and exposed to a bottom of said insulating board where said wiring is formed.
    Type: Application
    Filed: January 21, 2003
    Publication date: September 25, 2003
    Inventors: Akira Chinda, Akira Matsuura, Takayuki Yoshiwa, Mamoru Mita, Takashi Kageyama, Katsutoshi Taga
  • Patent number: 6506627
    Abstract: A structure of a semiconductor device of a chip scale package structure is provided. In the semiconductor device, the limitation to size reduction due to the bonding tool is small and the bonding pitch of the semiconductor chip can be reduced to 100 &mgr;m or less, and the chip shrink technique of a technique for lowering the cost can be employed and in connection with this compatibility among packages can be kept.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: January 14, 2003
    Assignee: Hitachi Cable, Ltd.
    Inventors: Gen Murakamz, Mamoru Mita, Norio Okabe, Yasuharu Kameyama
  • Publication number: 20020158343
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 proved on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 31, 2002
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Publication number: 20020160185
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Application
    Filed: May 6, 2002
    Publication date: October 31, 2002
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6433409
    Abstract: A semiconductor device, comprising: a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion; an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion; and a molding resin for sealing said joined portion including the solder, wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin, the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa, and the solder compri
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: August 13, 2002
    Assignee: Hitachi Cable Ltd.
    Inventors: Mamoru Mita, Gen Murakami