Abstract: A child station (3) of a communication system performs communication while synchronizing the reference time of a parent station (2) with the local time (RT) of the child station (3). When the child station (3) is switched from a normal mode to a power saving mode in accordance with a mode change instruction from the parent station (2), correction is performed for one or both of a stop period in which the apparatus of the child station (3) is stopped and a non-stop period in the power saving mode using an error (?t) generated during the time between the reference time of the parent station (2) and the local time (RT) of the child station (3). This makes it possible to synchronize the parent station (2) with the child station (3) and reliably and efficiently transfer a control frame (CF) from the parent station (2) to the child station (3).

Abstract: Identifier information (LLID) of an ONU and transfer instruction information indicating a transmission system as the output destination of a downstream frame are registered in a table (22) in correspondence with each of the destination IDs of the ONUs or user apparatuses connected to the ONUs. Upon receiving a downstream frame from a host apparatus, a frame transfer processing unit (20) acquires an LLID and transfer instruction information corresponding to the destination ID of the downstream frame from the table (22).

Abstract: Out of one constantly fed block (B0) and one power saving block (B1) provided by dividing in advance circuit units constituting an OLT (10), a power supply control unit (40) constantly supplies power to circuit units belonging to the constantly fed block. For circuit units belonging to the power saving block, the power supply control unit starts power supply to the power saving block starts in synchronism with the start of the period of an upstream bandwidth allocated to each ONU, and stops the power supply to the power saving block in synchronism with the end of the period of the upstream bandwidth. The power supply control unit starts power supply at a timing specified based on the start timing of the upstream bandwidth, and stops the power supply at a timing decided based on the end timing of the upstream bandwidth. This reduces the power consumption of an overall OLT.

Abstract: A child station (3) of a communication system performs communication while synchronizing the reference time of a parent station (2) with the local time (RT) of the child station (3). When the child station (3) is switched from a normal mode to a power saving mode in accordance with a mode change instruction from the parent station (2), correction is performed for one or both of a stop period in which the apparatus of the child station (3) is stopped and a non-stop period in the power saving mode using an error (?t) generated during the time between the reference time of the parent station (2) and the local time (RT) of the child station (3). This makes it possible to synchronize the parent station (2) with the child station (3) and reliably and efficiently transfer a control frame (CF) from the parent station (2) to the child station (3).

Abstract: Identifier information (LLID) of an ONU and transfer instruction information indicating a transmission system as the output destination of a downstream frame are registered in a table (22) in correspondence with each of the destination IDs of the ONUs or user apparatuses connected to the ONUs. Upon receiving a downstream frame from a host apparatus, a frame transfer processing unit (20) acquires an LLID and transfer instruction information corresponding to the destination ID of the downstream frame from the table (22).

Abstract: This invention includes an image quality priority level decision processing unit (40) which evaluates the magnitude of an image quality of each of a plurality of first image data formed from biometric images associated with the same target on the basis of a specific index having the relationship of a monotone function with authentication accuracy of biometric authentication, and outputs each of the first image data upon adding a priority level thereto on the basis of the evaluation result, a first image storage (6, 81) unit which stores each of the first image data having a priority level added thereto from the image quality priority level decision processing unit (40), a second image storage unit (8, 61) which stores second image data used for comparison/collation with the first image data, an image collation unit (7) which compares/collates the second image data stored in the second image storage unit (8, 61) with the first image data stored in the first image storage unit (6, 81) and outputs the comparison

Abstract: A sensor cell includes a sensor electrode (101) formed on a substrate (100), a signal output unit (16) which outputs a signal corresponding to a capacitance (Cf) formed between the sensor electrode and the surface of a finger (3), a high-sensitivity electrode (103) formed on the substrate so as to be insulated and isolated from the sensor electrode, and a potential controller (14) which controls the potential of the finger surface via a capacitance (Cc) formed between the high-sensitivity electrode and the finger surface by controlling the potential of the high-sensitivity electrode. In this arrangement, when the resistance of the finger is high, the potential of the finger surface can be controlled so as not to fluctuate with the potential change of the sensor electrode.

Abstract: A parallel processing logic circuit for sensor signal processing includes sensors and processing units. The sensor and the processing unit are integrated in the same pixel and arranged in a matrix. The processing unit contains a logic structure that consists of a register and a combinational logic function to execute pixel-parallel processing, based on binary data for a sensor, other processing units, and itself. The combinational logic function performs only a predetermined logic function and its dual one exclusively, thereby sharing the circuit resource and reducing the size of the processing unit. The register focusing on compactness also contributes to the small unit.

Abstract: A sensor cell includes a sensor electrode (101) formed on a substrate (100), a signal output unit (16) which outputs a signal corresponding to a capacitance (Cf) formed between the sensor electrode and the surface of a finger (3), a high-sensitivity electrode (103) formed on the substrate so as to be insulated and isolated from the sensor electrode, and a potential controller (14) which controls the potential of the finger surface via a capacitance (Cc) formed between the high-sensitivity electrode and the finger surface by controlling the potential of the high-sensitivity electrode. In this arrangement, when the resistance of the finger is high, the potential of the finger surface can be controlled so as not to fluctuate with the potential change of the sensor electrode.

Abstract: A certificate authority for certifying the validity of the collation result from a user terminal is placed on a communication network. The user terminal identifies a user himself or herself by collation by using biometrical information of the user. In response to notification of the collation result from the user terminal across the communication network, a service providing apparatus requests across the communication network the certificate authority to certify the validity of the collation result. When a certificate which certifies the validity of the collation result is notified from the certificate authority across the communication network, the service providing apparatus provides a predetermined service to the user.

Abstract: An image processing apparatus includes an image correcting section. When an image of an object is input, the image correcting section performs correction processing for the input image including the object image and outputs the corrected image as an image required for authentication of the object. An image processing method is also disclosed.

Abstract: An image collation apparatus includes a collation unit, minimum coincidence ratio extraction unit, and determination unit. The collation unit obtains a coincidence ratio between first and second images within a printing element range for each collation unit by collating the first and second images with each other. The minimum coincidence ratio extraction unit obtains a minimum coincidence ratio from coincidence ratios obtained from the collation unit. The determination unit determines that the first and second images are identical, if the extracted minimum coincidence ratio is smaller than a predetermined threshold. An image collation method is also disclosed.

Abstract: An image collation apparatus includes a collation unit, minimum coincidence ratio extraction unit, and determination unit. The collation unit obtains a coincidence ratio between first and second images within a printing element range for each collation unit by collating the first and second images with each other. The minimum coincidence ratio extraction unit obtains a minimum coincidence ratio from coincidence ratios obtained from the collation unit. The determination unit determines that the first and second images are identical, if the extracted minimum coincidence ratio is smaller than a predetermined threshold. An image collation method is also disclosed.

Abstract: A control apparatus has a momentary switch. In response to an operation performed on a momentary switch, a latch circuit (13) switches a latch output signal to be outputted to a microcomputer (11) from “high” to “low” and keeps the latch output signal “low”. A capacitor (C) supplies an electric power to the latch circuit (13) when supply of the electric power is cut off. A reset circuit (15) sends a signal to the latch circuit (13) in response to an input of a high-level latch reset signal from the microcomputer (11) so that the latch circuit (13) switches the latch output signal from “low” to “high”. If the latch output signal is “high” when the microcomputer (11) detects that the switch (SW) is operated, a transistor (Tr) is turned on under the control of the microcomputer (11). If the latch output signal is “low” when the microcomputer (11) detects that the switch (SW) is operated, the transistor (Tr) is turned off under the control of the microcomputer (11).

Abstract: This invention includes an image quality priority level decision processing unit (40) which evaluates the magnitude of an image quality of each of a plurality of first image data formed from biometric images associated with the same target on the basis of a specific index having the relationship of a monotone function with authentication accuracy of biometric authentication, and outputs each of the first image data upon adding a priority level thereto on the basis of the evaluation result, a first image storage (6, 81) unit which stores each of the first image data having a priority level added thereto from the image quality priority level decision processing unit (40), a second image storage unit (8, 61) which stores second image data used for comparison/collation with the first image data, an image collation unit (7) which compares/collates the second image data stored in the second image storage unit (8, 61) with the first image data stored in the first image storage unit (6, 81) and outputs the comparison

Abstract: An image processing apparatus includes an image correcting section. When an image of an object is input, the image correcting section performs correction processing for the input image including the object image and outputs the corrected image as an image required for authentication of the object. An image processing method is also disclosed.

Abstract: A control apparatus has a momentary switch. In response to an operation performed on a momentary switch, a latch circuit (13) switches a latch output signal to be outputted to a microcomputer (11) from “high” to “low” and keeps the latch output signal “low”. A capacitor (C) supplies an electric power to the latch circuit (13) when supply of the electric power is cut off. A reset circuit (15) sends a signal to the latch circuit (13) in response to an input of a high-level latch reset signal from the microcomputer (11) so that the latch circuit (13) switches the latch output signal from “low” to “high”. If the latch output signal is “high” when the microcomputer (11) detects that the switch (SW) is operated, a transistor (Tr) is turned on under the control of the microcomputer (11).

Abstract: A parallel processing logic circuit for sensor signal processing includes sensors and processing units. The sensor and the processing unit are integrated in the same pixel and arranged in a matrix. The processing unit contains a logic structure that consists of a register and a combinational logic function to execute pixel-parallel processing, based on binary data for a sensor, other processing units, and itself. The combinational logic function performs only a predetermined logic function and its dual one exclusively, thereby sharing the circuit resource and reducing the size of the processing unit. The register focusing on compactness also contributes to the small unit.

Abstract: A certificate authority for certifying the validity of the collation result from a user terminal is placed on a communication network. The user terminal identifies a user himself or herself by collation by using biometrical information of the user. In response to notification of the collation result from the user terminal across the communication network, a service providing apparatus requests across the communication network the certificate authority to certify the validity of the collation result.

Abstract: A method for measuring activity of osteoclast-derived acid phosphatase located at Band 5b of Band 5 in polyacrylamide gel electrophoresis of a sample which is characterized by using an inhibitor to acid phosphatases located at Band 5 other than Band 5b; and a composition and a kit for using in the method.