Patents by Inventor Mamoru Ohba
Mamoru Ohba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230090474Abstract: A vehicle control device causes an automatic brake to function even for an obstacle suddenly appearing from outside a sensor detection range in a place estimated to be dangerous such as an intersection. A vehicle control device calculates time-to-collision TTC based on a detection result of an obstacle sensor, and controls a brake, which is an actuator of a vehicle, based on the calculated time-to-collision TTC. The vehicle control device includes a determination unit that determines right turn or left turn of the vehicle, and a command unit that sends a command according to a determination result of the determination unit to the brake. When determining that the vehicle is turning right or left, the determination unit changes the time-to-collision TTC to a longer value by extending more than that at the time of traveling straight.Type: ApplicationFiled: December 18, 2020Publication date: March 23, 2023Applicant: Hitachi Astemo, Ltd.Inventors: Mamoru OHBA, Toshiyuki INNAMI, Koichi YOKOURA
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Patent number: 6677950Abstract: To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and 2 multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes 2 line drawing procedure that uses data tables and 2 multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data.Type: GrantFiled: December 22, 1997Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Mamoru Ohba, Mitsuru Watabe, Rika Minami, Koyo Katsura
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Publication number: 20030042144Abstract: A high-frequency circuit device using a plane antenna is provided which has improved reliability of electrical conduction even when subjected to repeated bending stresses. A film structure of a wiring pattern is constituted by forming a Cu-film layer on an organic substrate, and then forming a Ni-plated film and an Au-plated film successively on the Cu-film layer. The Ni-plated film is formed by electrolytic plating. An elongation rate of the Ni-plated film formed by electrolytic plating is 4.9% at minimum. A thermal shock test proves that the wiring pattern is free from cracks and disconnections. Hence, reliability against repeated bending stresses can be improved.Type: ApplicationFiled: February 27, 2002Publication date: March 6, 2003Applicant: Hitachi, Ltd.Inventors: Tadashi Isono, Terumi Nakazawa, Shirou Oouchi, Yoshiyuki Sasada, Mamoru Ohba
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Patent number: 5771047Abstract: To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and a multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes a line drawing procedure that uses data tables and a multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data.Type: GrantFiled: December 14, 1994Date of Patent: June 23, 1998Assignee: Hitachi, Ltd.Inventors: Mamoru Ohba, Mitsuru Watabe, Rika Minami, Koyo Katsura
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Patent number: 5642499Abstract: In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.Type: GrantFiled: April 6, 1994Date of Patent: June 24, 1997Assignee: Hitachi, Ltd.Inventors: Mamoru Ohba, Shigeki Morinaga, Mitsuru Watabe, Hiroyuki Kida
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Patent number: 5504912Abstract: The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.Type: GrantFiled: February 5, 1992Date of Patent: April 2, 1996Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Shigeki Morinaga, Norio Nakagawa, Mitsuru Watabe, Mamoru Ohba, Hiroyuki Kida, Hisashi Kaziwara, Takeshi Asai, Junichi Tatezaki
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Patent number: 5289517Abstract: A digital pulse processing device is capable of selecting desired precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters A and B that can be separated from and coupled with each other, a mode control circuit for instructing separation and coupling of the counters A and B, and a control circuit for separating and coupling the counters A and B in accordance with the instruction of the mode control circuit. An overflow condition of the free-run counter B is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow.Type: GrantFiled: September 10, 1991Date of Patent: February 22, 1994Assignee: Hitachi, Ltd.Inventors: Mamoru Ohba, Mitsuru Watabe, Rika Minami, Sanshiro Obara