Patents by Inventor Mamoru Sakamoto

Mamoru Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200151778
    Abstract: Provided is a matching support system including a matching support device, which includes a storage device storing predetermined conditions specified for an output of a molded object by each of an agency of the output of the molded object, a provider of 3D printer data, and an end user wanting the molded object that are parties of an output business of the molded object by a 3D printer, and a computing device comparing each condition of the party at least based on the respective contents of the molded object, the 3D printer, and cost which are specified under a condition of the end user, using the 3D printer data necessary for the output of the molded object, specifying the agency satisfying the condition of the end user, and outputting information on the agency to a predetermined device.
    Type: Application
    Filed: July 17, 2018
    Publication date: May 14, 2020
    Inventors: Takuya NAKAMURA, Mamoru SAKAMOTO, Masahiro TAKESHIMA
  • Patent number: 8487950
    Abstract: An overflow suppression technique that is effective for avoiding degradation in image quality is provided. A fundamental waveform and detail is extracted out of an input RGB signal. A suppression gain generation unit 614 generates a suppression gain from the extracted fundamental waveform. Multipliers 612a and 612b multiply the detail and the fundamental waveform by the generated suppression gain, respectively. Then, an adder 626 combines them together for a mixed output. Alternatively, equalization processing is performed as follows. A low frequency component fundamental waveform is obtained as a result of the passing of an input RGB signal through a low pass filter 622. A suppression gain is generated from the low frequency component fundamental waveform. Then, the input itself is multiplied by the suppression gain to obtain an output.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: July 16, 2013
    Assignees: Taiyo Yuden Co. Ltd., Microspace Corporation
    Inventors: Masato Tanaka, Kazuo Asanuma, Mamoru Sakamoto, Yasuo Hosaka, Akinobu Maekawa, Hidehumi Nakagome
  • Publication number: 20120076418
    Abstract: To provide a face attribute estimating apparatus capable of determining a face attribute with high precision. A scan region extracting part extracts, as a scan region, a region in which a specific face part can exist from a face region detected by a face detecting part. A region scanning part sets a small region in the scan region extracted by the scan region extracting part and, while scanning the scan region with the small region, sequentially outputs a pixel value in the small region. A pattern similarity calculating part sequentially calculates similarity between the pixel value output from the region scanning part and a specific pattern on the specific face part. A face attribute determining part determines a face attribute by comprehensively determining the similarities sequentially calculated by the pattern similarity calculating part. Therefore, a face attribute can be determined with high precision.
    Type: Application
    Filed: July 20, 2011
    Publication date: March 29, 2012
    Inventors: Yukiyoshi SASAO, Mamoru Sakamoto
  • Publication number: 20100259689
    Abstract: An overflow suppression technique that is effective for avoiding degradation in image quality is provided. A fundamental waveform and detail is extracted out of an input RGB signal. A suppression gain generation unit 614 generates a suppression gain from the extracted fundamental waveform. Multipliers 612a and 612b multiply the detail and the fundamental waveform by the generated suppression gain, respectively. Then, an adder 626 combines them together for a mixed output. Alternatively, equalization processing is performed as follows. A low frequency component fundamental waveform is obtained as a result of the passing of an input RGB signal through a low pass filter 622. A suppression gain is generated from the low frequency component fundamental waveform. Then, the input itself is multiplied by the suppression gain to obtain an output.
    Type: Application
    Filed: October 27, 2008
    Publication date: October 14, 2010
    Inventors: Masato Tanaka, Kazuo Asanuma, Mamoru Sakamoto, Yasuo Hosaka, Akinobu Maekawa, Hidehumi Nakagome
  • Patent number: 7408306
    Abstract: The present invention relates to a lamp lighting technique for lighting multiple lamps safely without luminance irregularities. The present lamp lighting circuit includes multiple closed loops wherein a predetermined number of lamps and the secondary windings of the predetermined number of transformers are connected serially. At least one of the primary windings of the transformers employed for each closed loop is connected to the primary winding of the transformer employed for another closed loop serially. Thus, current of the lamps included in the closed loop is made uniform, and also current is made uniform even between the closed loops by connecting the primary windings of the transformers serially. According to the present invention, with regard to serial connection of the primary windings of the transformers, even if the number of transformers is limited, current uniformity can be propagated to the entirety by subjecting closed loops to catenation consecutively.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: August 5, 2008
    Assignees: Taiyo Yuden, Ltd., Microspace Corporation
    Inventors: Masato Tanaka, Yasuo Hosaka, Mamoru Sakamoto, Akinobu Maekawa, Hidefumi Nakagome
  • Patent number: 7143274
    Abstract: An interrupt controlling method is provided that is capable of executing an interrupt process while avoiding slowing-down in execution speed of a task process. When an interrupt request occurs while a task processing program is being executed, the task processing program is suspended and execution of an interrupt handler is started. By the interrupt handler, a plurality of breakpoints are set in an interrupt process-enabled area (R2). Execution of the resumed task processing program soon reaches one of the plurality of breakpoints. Then, the microprocessor (1) suspends the execution of the task processing program and starts execution of a breakpoint handler. By the breakpoint handler, the interrupt process is executed, and thereafter, the settings of the breakpoints are cleared.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: November 28, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Mamoru Sakamoto
  • Publication number: 20060132059
    Abstract: The present invention relates to a lamp lighting technique for lighting multiple lamps safely without luminance irregularities. The present lamp lighting circuit includes multiple closed loops wherein a predetermined number of lamps and the secondary windings of the predetermined number of transformers are connected serially. At least one of the primary windings of the transformers employed for each closed loop is connected to the primary winding of the transformer employed for another closed loop serially. Thus, current of the lamps included in the closed loop is made uniform, and also current is made uniform even between the closed loops by connecting the primary windings of the transformers serially. According to the present invention, with regard to serial connection of the primary windings of the transformers, even if the number of transformers is limited, current uniformity can be propagated to the entirety by subjecting closed loops to catenation consecutively.
    Type: Application
    Filed: August 5, 2005
    Publication date: June 22, 2006
    Inventors: Masato Tanaka, Yasuo Hosaka, Mamoru Sakamoto, Akinobu Maekawa, Hidefumi Nakagome
  • Patent number: 7065751
    Abstract: A program execution device with a small required memory storage capacity includes: a compressed code storing portion storing a code which has been compressed on a prescribed unit basis of a program described in a prescribed language; an expanding portion connected to the compressed code storing portion for expanding the compressed code stored in the compressed code storing portion; a code storing portion connected to the expanding portion for storing the code expanded by the expanding portion; and an interpreter portion connected to the code storing portion for interpreting and executing the expanded code.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: June 20, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Masato Hagiwara, Toyohiko Yoshida, Mamoru Sakamoto
  • Patent number: 6958593
    Abstract: This invention provides a stable power supply apparatus enabling the high speed response. Hitherto, it was necessary to secure both of the gain margin and the phase margin on the Bode diagram of the loop transfer function when the PID feedback control was carried out in the power supply apparatus. The form of the transfer function of the controller in the power supply apparatus of this invention is the same, but a set of coefficient values in the transfer function is completely different, and the controller secures only the phase margin without securing the gain margin. Furthermore, the transfer function of the controller indicates a part with an extreme decrease in the gain and a trap point in which the phase is sharply delayed on the Bode diagram. This is achieved by applying the integral element of the PID to a frequency range that is higher than the resonance frequency of the LC filter. As a result, the high speed response becomes possible without losing the stability.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: October 25, 2005
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Kazuo Asanuma, Mamoru Sakamoto
  • Patent number: 6871259
    Abstract: A flash memory includes a data bank having a plurality of banks, a merge bank, and an update data bank. A file system using the flash memory includes a unit storing update data corresponding to a data rewrite command into the update data bank, a unit selecting the latest update data for each block from update data stored in the update data bank when the update data bank becomes full, and a processing unit processing the latest update data. The processing unit includes a unit storing latest update data into a merge bank, a unit selecting data associated with the latest update data from the data bank to store the selected data into the merge bank, and a unit setting the merge bank as a new data bank.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: March 22, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masato Hagiwara, Mamoru Sakamoto
  • Patent number: 6820252
    Abstract: A data processor includes a hardware translator converting non-native code into a native code to a processor, a software translator converting non-native code into a native code to the processor by software, and a software interpreter sequentially interpreting a code that is non-native to the processor, and executing the interpreted code using a native code of the processor. The data processor includes a circuit selecting the hardware translator, software translator or software interpreter according to a predetermined criterion for operation.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: November 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Mamoru Sakamoto, Toyohiko Yoshida
  • Publication number: 20040181793
    Abstract: An interrupt controlling method is provided that is capable of executing an interrupt process while avoiding slowing-down in execution speed of a task process. When an interrupt request occurs while a task processing program is being executed, the task processing program is suspended and execution of an interrupt handler is started. By the interrupt handler, a plurality of breakpoints are set in an interrupt process-enabled area (R2). Execution of the resumed task processing program soon reaches one of the plurality of breakpoints. Then, the microprocessor (1) suspends the execution of the task processing program and starts execution of a breakpoint handler. By the breakpoint handler, the interrupt process is executed, and thereafter, the settings of the breakpoints are cleared.
    Type: Application
    Filed: October 1, 2003
    Publication date: September 16, 2004
    Applicant: Renesas Technology Corp.
    Inventor: Mamoru Sakamoto
  • Publication number: 20040100238
    Abstract: This invention provides a stable power supply apparatus enabling the high speed response. Hitherto, it was necessary to secure both of the gain margin and the phase margin on the Bode diagram of the loop transfer function when the PID feedback control was carried out in the power supply apparatus. The form of the transfer function of the controller in the power supply apparatus of this invention is the same, but a set of coefficient values in the transfer function is completely different, and the controller secures only the phase margin without securing the gain margin. Furthermore, the transfer function of the controller indicates a part with an extreme decrease in the gain and a trap point in which the phase is sharply delayed on the Bode diagram. This is achieved by applying the integral element of the PID to a frequency range that is higher than the resonance frequency of the LC filter. As a result, the high speed response becomes possible without losing the stability.
    Type: Application
    Filed: November 3, 2003
    Publication date: May 27, 2004
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Kazuo Asanuma, Mamoru Sakamoto
  • Publication number: 20040015895
    Abstract: A program execution device with a small required memory storage capacity includes: a compressed code storing portion storing a code which has been compressed on a prescribed unit basis of a program described in a prescribed language; an expanding portion connected to the compressed code storing portion for expanding the compressed code stored in the compressed code storing portion; a code storing portion connected to the expanding portion for storing the code expanded by the expanding portion; and an interpreter portion connected to the code storing portion for interpreting and executing the expanded code.
    Type: Application
    Filed: February 13, 2002
    Publication date: January 22, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masato Hagiwara, Toyohiko Yoshida, Mamoru Sakamoto
  • Publication number: 20030110343
    Abstract: A flash memory includes a data bank having a plurality of banks, a merge bank, and an update data bank. A file system using the flash memory includes a unit storing update data corresponding to a data rewrite command into the update data bank, a unit selecting the latest update data for each block from update data stored in the update data bank when the update data bank becomes full, and a processing unit processing the latest update data. The processing unit includes a unit storing latest update data into a merge bank, a unit selecting data associated with the latest update data from the data bank to store the selected data into the merge bank, and a unit setting the merge bank as a new data bank.
    Type: Application
    Filed: June 12, 2002
    Publication date: June 12, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masato Hagiwara, Mamoru Sakamoto
  • Publication number: 20020099930
    Abstract: A data processor includes a hardware translator converting non-native code into a native code to a processor, a software translator converting non-native code into a native code to the processor by software, and a software interpreter sequentially interpreting a code that is non-native to the processor, and executing the interpreted code using a native code of the processor. The data processor includes a circuit selecting the hardware translator, software translator or software interpreter according to a predetermined criterion for operation.
    Type: Application
    Filed: November 29, 2001
    Publication date: July 25, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mamoru Sakamoto, Toyohiko Yoshida
  • Patent number: 6348755
    Abstract: It is an object of the present invention to provide a method and an apparatus for driving a piezoelectric transformer capable of always driving with maximum conversion efficiency regardless of changes in the input voltage level, load and temperature, etc.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: February 19, 2002
    Assignee: Taiyo Yuden, Co., Ltd.
    Inventors: Junichi Shimamura, Mamoru Sakamoto, Kenji Kamitani
  • Patent number: 6279079
    Abstract: A duplicate of a function code is created in a fast memory contiguous with a normal memory so that a CPU checks whether the duplicate is located in the fast memory when the function code is called; and a block containing a function code may be released so as to create therein a duplicate of a new function code.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: August 21, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Mamoru Sakamoto
  • Patent number: 6130833
    Abstract: A power source 1 and an operating circuit 4 incorporating a waveform generating circuit 5 for synthesizing composite wave W obtained by synthesizing a sine wave of primary oscillations and a sine wave of secondary oscillations of a Rosen-type piezoelectric transformer and an amplifying circuit 6 raises the voltage of the composite wave so that composite wave W' (having a waveform similar to that of W) is, as input voltage V.sub.in, supplied to the Rosen-type piezoelectric transformer PT. Thus, output voltage V.sub.out having greater output electric power and higher transmitting efficiencies as compared with output voltage which can be obtained from a conventional structure in which input voltage in a single oscillation mode is employed can be produced to load resistor R.sub.o.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: October 10, 2000
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Mamoru Sakamoto, Junichi Shimamura
  • Patent number: 5813691
    Abstract: A twist beam type suspension has a twist beam having an increased rigidity. Each of a pair of trailing arms has a front end pivotally mounted on a body of the vehicle and a rear end rotatably supporting a wheel. A twist beam extends between the trailing arms in a side-to-side direction of the vehicle. Opposite ends of the twist beam are connected to the respective trailing arms. The twist beam has a bent portion projecting upwardly in the center of the twist beam.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: September 29, 1998
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tetsuya Aoki, Yoji Uchida, Mamoru Sakamoto, Toshiyasu Santo, Tatsuzo Komiya, Masaharu Ohba