Patents by Inventor Mamoru Sugie
Mamoru Sugie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070203950Abstract: A storage comprising an object access module for the shared part for implementing advanced I/O provides an interface for registering and deleting object description data declaring how to store objects within a second storage, in order to reduce the development cost of modules for implementing functions. Also, in order to reduce the total cost of ownership, modules are transferred to the storage through a management computer. The present invention allows the storage for contiguously providing functions effective to a vast range of applications to be provided with lower development cost as well as lower total cost of ownership.Type: ApplicationFiled: May 1, 2007Publication date: August 30, 2007Inventors: Shigekazu Inohara, Itaru Nishizawa, Naoki Watanabe, Aki Tomita, Frederico Maciel, Hiroaki Odawara, Nobutoshi Sagawa, Mamoru Sugie
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Patent number: 7231401Abstract: A storage comprising an object access module for the shared part for implementing advanced I/O provides an interface (121) for registering and deleting object description data declaring how to store objects within a second storage, in order to reduce the development cost of modules for implementing functions. Also, in order to reduce the total cost of ownership, modules are transferred to the storage through a management computer. The present invention allows the storage for contiguously providing functions effective to a vast range of applications to be provided with lower development cost as well as lower total cost of ownership.Type: GrantFiled: October 13, 1999Date of Patent: June 12, 2007Assignee: Hitachi, Ltd.Inventors: Shigekazu Inohara, Itaru Nishizawa, Naoki Watanabe, Aki Tomita, Frederico Buchholz Maciel, Hiroaki Odawara, Nobutoshi Sagawa, Mamoru Sugie
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Patent number: 6519598Abstract: A data request analysis unit for accepting and analyzing a request from a client computer, a data conversion program generation unit, and a data conversion unit are provided in a magnetic disk apparatus, the data conversion program generation unit downloads a program module by way of a network as required based on the analysis result obtained by use of the data request analysis unit to generate a data conversion program, and the data conversion unit downloads the conversion program, and converts the type of the data read out from the magnetic memory medium by use of the program, and directly transfers the converted data to the client computer by way of a network interface, thereby, the present invention provides a general purpose magnetic disk apparatus which is capable of flexibly accommodating the request from the client computer, the scalability of the whole system is improved because the data is converted in the magnetic disk apparatus, and the process efficiency of the client computer is improved.Type: GrantFiled: August 25, 1999Date of Patent: February 11, 2003Assignee: Hitachi, Ltd.Inventors: Itaru Nishizawa, Mamoru Sugie, Nobutoshi Sagawa, Hiroaki Odawara, Shigekazu Inohara, Frederico Maciel, Naoki Watanabe, Aki Tomita
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Patent number: 4910667Abstract: In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided.Type: GrantFiled: April 22, 1988Date of Patent: March 20, 1990Assignee: Hitachi, Ltd.Inventors: Teruo Tanaka, Koichiro Omoda, Yasuhiro Inagami, Takayuki Nakagawa, Mamoru Sugie, Shigeo Nagashima
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Patent number: 4607178Abstract: A semiconductor integrated circuit receiving at its input pin the terminal voltage of a capacitor which is connected to a power source through a resistor so as to detect the level of the power voltage. The circuit is provided with a level shift circuit which shifts the incoming power voltage level by a predetermined value so that a reset signal is produced by detecting the output of the level shift circuit falling below the threshold level of a logic circuit.Type: GrantFiled: August 3, 1983Date of Patent: August 19, 1986Assignee: Hitachi, Ltd.Inventors: Mamoru Sugie, Takashi Toyooka, Hirokazu Aoki, Kazutoshi Yoshida, Shinsaku Chiba
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Patent number: 4592016Abstract: A magnetic bubble memory device comprises a plurality of minor loops for storage of data information and a map loop for storage of defective-loop information, etc. The number of bits of the map loop is selected to be N times as large as the number of bits of each minor loop, N being an integer not smaller than 2.Type: GrantFiled: December 2, 1983Date of Patent: May 27, 1986Assignee: Hitachi, Ltd.Inventors: Yoshihiro Sekiguchi, Kazutoshi Yoshida, Shinsaku Chiba, Mamoru Sugie, Hirokazu Aoki
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Patent number: 4538242Abstract: A signal processing circuit for a magnetic bubble memory device is arranged to set a reference level for determining the level of "1" or "0" of the bubble sensing line signal during a period in which only a read signal corresponding to level "0" appears as the output signal of a differential amplifier of the bubble detector circuit.Type: GrantFiled: July 6, 1983Date of Patent: August 27, 1985Inventors: Takashi Toyooka, Aoki Hirokazu, Mamoru Sugie, Yutaka Sugita
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Patent number: 4530070Abstract: A magnetic bubble memory device including a magnetic bubble chip of major-minor structure is disclosed in which an integer m prime to the number n of bits of a minor loop is selected from integers i satisfying an equation i=(2.sup..alpha. .+-.1).multidot.2.sup..beta. +1 or i=(2.sup..alpha. .+-.1).multidot.2.sup..beta., and logical addresses on the minor loop are assigned in such a manner that adjacent logical addresses are spaced apart from each other by m bits.Type: GrantFiled: June 17, 1983Date of Patent: July 16, 1985Assignee: Hitachi, Ltd.Inventors: Mamoru Sugie, Takashi Toyooka, Hirokazu Aoki
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Patent number: 4519049Abstract: A magnetic bubble memory has a plurality of minor loops for storing data represented by magnetic bubble sequences, a write line for transferring write data to couple them to the minor loops and a read line for transferring read data to a bubble detector. The read line is coupled to a plurality of auxiliary loops through replicators and the auxiliary loops are coupled to the minor loops through replicators. The data replicated to the auxiliary loops are read out.Type: GrantFiled: December 3, 1982Date of Patent: May 21, 1985Assignee: Hitachi, Ltd.Inventors: Takashi Toyooka, Hirokazu Aoki, Mamoru Sugie
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Patent number: 4484309Abstract: A magnetic bubble memory device is provided with a plurality of memory modules each having at least one magnetic bubble chip. Each module generates a clock for determining the timing to drive the magnetic bubble chip and controls the operation of the magnetic bubble chip. The addresses of a main memory are cyclically allocated to the memory modules in a given unit, so that data transmission can be performed between the memory modules operated asynchronously with each other and the main memory allocated thereto.Type: GrantFiled: August 19, 1982Date of Patent: November 20, 1984Assignee: Hitachi, Ltd.Inventors: Mamoru Sugie, Takashi Toyooka, Hirokazu Aoki, Kazuya Kamiyama
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Patent number: 4430729Abstract: A series resonant drive circuit for a magnetic bubble memory includes X- and Y-coils arranged orthogonally to each other for generating a rotating magnetic field applied to a magnetic bubble memory chip, resonance capacitors each connected to a corresponding one of the X- and Y-coils for forming a series resonance circuit with the corresponding coil at a frequency of the rotating magnetic field, power supplies each connected to a corresponding one of the resonance circuits, and an inductance device connected in series with both of the resonance circuits and a capacitance device connected between the resonance circuits to compensate a mutual inductance due to the inductive coupling between the X- and Y-coils and a capacitance due to the capacitive coupling between the X- and Y-coils. Further, the temperature coefficient of the capacitance device is selected so that the temperature coefficients of the mutual inductance and capacitance between the coils can be compensated.Type: GrantFiled: September 8, 1982Date of Patent: February 7, 1984Assignee: Hitachi, Ltd.Inventors: Takashi Toyooka, Hirokazu Aoki, Mamoru Sugie, Shigeru Yoshizawa
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Patent number: 4379341Abstract: A series resonance drive circuit for a magnetic bubble memory comprises a magnetic bubble memory chip or chips, X and Y coils arranged orthogonally to each other to form a rotating magnetic field in a plane of the chip or chips, resonance capacitors connected in series with the X and Y coils to form series resonance circuits with the X and Y coils at a frequency of the rotating magnetic field, A.C. power supplies connected to the resonance circuit, and a reactance device connected to the resonance circuits to compensate a mutual inductance due to a mutual inductive coupling between the X and Y coils and a capacitance due to a capacitive coupling between the X and Y coils. The reactance device includes a mutual inductance device, or an inductance device and a capacitance device.Type: GrantFiled: September 18, 1981Date of Patent: April 5, 1983Assignee: Hitachi, Ltd.Inventors: Takashi Toyooka, Mamoru Sugie, Hirokazu Aoki, Shigeru Yoshizawa
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Patent number: 4291241Abstract: A timing signal generating circuit including a clock source which generates clock pulses of a predetermined period, a binary counter which divides the frequency of the clock pulses from the clock source by n, a logical array which decodes an output of the binary counter and which is composed of semiconductor elements and flip-flop circuits which are set or reset by outputs of the logical array in response to the clock pulses from the clock source with the outputs of the flip-flop circuits being used as timing signals.Type: GrantFiled: February 16, 1979Date of Patent: September 22, 1981Assignee: Hitachi, Ltd.Inventors: Koichi Mayama, Noboru Yamaguchi, Mamoru Sugie, Yuzo Kita, Shigeru Yoshizawa
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Patent number: 4290117Abstract: In a memory device which has a plurality of recirculating type storage loops and in which information of the same addresses of the respective storage loops can be read and written in parallel, a memory device wherein information representing whether or not the corresponding storage loop is a bad or defective loop is written in a specified address of each of the storage loops.Type: GrantFiled: February 21, 1979Date of Patent: September 15, 1981Assignee: Hitachi, Ltd.Inventors: Mamoru Sugie, Noboru Yamaguchi, Koichi Mayama, Yuzo Kita, Shigeru Yoshizawa, Nobuo Saito, Atsushi Asano
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Patent number: 4206968Abstract: A method for producing an optical fiber comprises (i) the step of depositing a barrier layer on the inner wall surface of a glass tube by the CVD (chemical vapor deposition) process, said barrier layer being capable of preventing the diffusion of impurities and being made of high-silica glass which has a refractive index that is substantially equal to that of the glass tube and which contains at least one substance for lowering the refractive index of silica and at least one substance for raising the refractive index of silica, (ii) the step of depositing a glass film of desired refractive index on the barrier layer by the CVD process, (iii) the step of heating and collapsing the resultant glass tube into a composite rod or the so-called optical fiber preform, and (iv) the step of heating and drawing said optical fiber preform into the optical fiber, whereby the optical fiber which has the impurity diffusion-preventing layer between the core and the outside glass layer can be easily produced.Type: GrantFiled: February 2, 1978Date of Patent: June 10, 1980Assignee: Hitachi, Ltd.Inventors: Tsuneo Suganuma, Gyozo Toda, Koji Ishida, Shin Satoh, Toshio Katsuyama, Mamoru Sugie
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Patent number: 4203743Abstract: A method of producing an optical fiber comprising (i) the step of depositing a glass film of desired refractive index onto the inner wall surface of a quartz tube by the CVD (chemical vapor deposition) process, (ii) the step of heating the quartz tube to a high temperature while the gas of a compound which forms an oxide, enhancing the refractive index of the glass film, in an oxidizing atmosphere at the high temperature is kept flowing into the quartz tube along with an oxidizing gas, (iii) the step of heating and collapsing the quartz tube into a solid rod or the so-called preform, and (iv) the step of heating and drawing the optical fiber preform into the optical fiber.In the optical fiber produced by this method of manufacture, the lowering of the refractive index of the central part of the optical fiber is sharply reduced.Type: GrantFiled: August 14, 1978Date of Patent: May 20, 1980Assignee: Hitachi, Ltd.Inventors: Tsuneo Suganuma, Koji Ishida, Shin Satoh, Mamoru Sugie, Toshio Katsuyama, Gyozo Toda