Abstract: An integrated circuit (IC), including a first integrated circuit (IC) cell configured to perform a defined operation on a first input signal to generate a first output signal, wherein the first IC cell includes a first metal configured to receive the first input signal or output the first output signal; and a second IC cell configured to perform the defined operation on a second input signal to generate a second output signal, wherein the second IC cell includes a second metal configured to receive the second input signal or the second output signal, wherein the second metal is located substantially in the same location within the second IC cell as the first metal is located within the first IC cell, and wherein the first and second metals are configured differently based on differences in first and second intercell metal interconnects to which the first and second metals electrically connect, respectively.

Abstract: An integrated circuit (IC), including a first integrated circuit (IC) cell configured to perform a defined operation on a first input signal to generate a first output signal, wherein the first IC cell includes a first metal configured to receive the first input signal or output the first output signal; and a second IC cell configured to perform the defined operation on a second input signal to generate a second output signal, wherein the second IC cell includes a second metal configured to receive the second input signal or the second output signal, wherein the second metal is located substantially in the same location within the second IC cell as the first metal is located within the first IC cell, and wherein the first and second metals are configured differently based on differences in first and second intercell metal interconnects to which the first and second metals electrically connect, respectively.

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract: Provided are systems and methods for reducing power consumption in the interface and routing circuitry associated with various core modules of an integrated circuit or system. One system includes core modules, glue logic domains adapted to interface the plurality of core modules, and a power controller electrically coupled to the glue logic domains. Each glue logic domain includes a glue logic module implemented as a soft macro with metal traces extending beyond an extent of the glue logic module. The power controller decouples power from selected glue logic domains based on control signals and/or detected power down states of core modules and/or other glue logic domains. The power controller facilitates the power transitions using logic state retention, logic state clamping, ordered or scheduled transitioning, and/or other power transition systems and methods.

Abstract: Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile peaks, sampling instantaneous current from individual tile-based current demand profiles at each time point, and running Static IR Analysis for the tiles at the time points to determine tile current use by the tiles during the time points. Enhanced Static IR Drop Analysis can be used for quick assessment of peak current distribution and determining how the peak current distribution stresses the power distribution network. Enhanced Static IR Drop Analysis is useful during earlier stages of circuit design, when quickly producing circuit performance data is imperative and conventional techniques require significant resources.

Abstract: Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile peaks, sampling instantaneous current from individual tile-based current demand profiles at each time point, and running Static IR Analysis for the tiles at the time points to determine tile current use by the tiles during the time points. Enhanced Static IR Drop Analysis can be used for quick assessment of peak current distribution and determining how the peak current distribution stresses the power distribution network. Enhanced Static IR Drop Analysis is useful during earlier stages of circuit design, when quickly producing circuit performance data is imperative and conventional techniques require significant resources.

Abstract: A single event upset (SEU) tolerant SRAM bit cell for six-transistor (6T), eight-transistor (8T), or multi-port RAM cell configurations fabricated in accordance with 0.18 &mgr;m or smaller CMOS processes. SEU tolerance is achieved without significantly increasing the cell's read and write cycle time and negligible impact on cell stability.