Abstract: A tubing hanger for supporting a tubing string from a wellhead includes a unified mandrel having an upper mandrel coupled to an axially aligned lower mandrel by multiple separate connections. The upper mandrel includes an external shoulder, and a lower mandrel includes a threaded segment configured to couple to the tubing string. The first connection is configured to restrain axial movement between the upper and lower mandrel and to transfer toque between the upper mandrel and the lower mandrel in at least a first rotational direction. The second connection is configured to transfer toque between them in at least a second rotational direction opposite the first rotational direction, to prevent the first connection from loosening.

Abstract: A tubing hanger for supporting a tubing string from a wellhead includes a unified mandrel having an upper mandrel coupled to an axially aligned lower mandrel by multiple separate connections. The upper mandrel includes an external shoulder, and a lower mandrel includes a threaded segment configured to couple to the tubing string. The first connection is configured to restrain axial movement between the upper and lower mandrel and to transfer toque between the upper mandrel and the lower mandrel in at least a first rotational direction. The second connection is configured to transfer toque between them in at least a second rotational direction opposite the first rotational direction, to prevent the first connection from loosening.

Abstract: Methods and apparatus to odd and even frame combination data path architectures are described. In one embodiment, a logic may include a buffer and a parallel input, serial output (PISO) logic that may be utilized for transferring data between a source and a destination. The logic may be utilized for transferring the data whether or not the data is transmitted in accordance with single ended or differential signals. Other embodiments are also described.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes a loop circuit to align an input clock signal with an output clock signal, and also aligns transmitted data with the output clock signal.

Abstract: In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct receipt of the predetermined data pattern in a buffer of the second agent, determining in a state machine of the first agent an updated load position within a window of the predetermined data pattern at which the buffer can realize the correct receipt, and transmitting the updated load position to the second agent to enable the second agent to capture incoming data from the first agent at the updated load position. Other embodiments are described and claimed.

Abstract: Methods and apparatus to odd and even frame combination data path architectures are described. In one embodiment, a logic may include a buffer and a parallel input, serial output (PISO) logic that may be utilized for transferring data between a source and a destination. The logic may be utilized for transferring the data whether or not the data is transmitted in accordance with single ended or differential signals. Other embodiments are also described.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct receipt of the predetermined data pattern in a buffer of the second agent, determining in a state machine of the first agent an updated load position within a window of the predetermined data pattern at which the buffer can realize the correct receipt, and transmitting the updated load position to the second agent to enable the second agent to capture incoming data from the first agent at the updated load position. Other embodiments are described and claimed.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations. The loop circuits include phase interpolators to produce local clock signals. Local clock signals are provided to seqiuential elements through local clock trees and are also provided to a phase detector through a dummy local clock tree. The operation of the phase interpolators is influenced by the phase detector.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate transmit and receive delay de-skew clock signals, a first set of phase interpolators to provide data transmit de-skewing and a first set of slave delay lines to provide data receive de-skewing.

Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate transmit and receive delay de-skew clock signals, a first set of phase interpolators to provide data transmit de-skewing and a first set of slave delay lines to provide data receive de-skewing.

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.

Abstract: A device includes a number of output circuits to drive a number of output signals. The output signals have timing relationship among each other. The device also includes a control loop circuit serving as a feedback loop to adjust any mismatch between the timing relationships of the output signals.

Abstract: A device includes an output circuit to output an output signal. The device also includes a control loop circuit to measure the real slew of the output signal. The control loop circuit compares the real slew with a target slew adjusts the output circuit when the real slew and the target are mismatched.

Abstract: A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.