Patents by Inventor Man Dieu Trinh

Man Dieu Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150334034
    Abstract: Systems and methods accessing remote digital data over a wide area network (WAN) are disclosed. In an embodiment, a network device is disclosed. The network device includes a local area network (LAN) switching fabric physical interface configured to communicate according to a LAN switching fabric protocol, a WAN physical interface configured to communicate according to a WAN protocol, and a fabric extension function configured to map LAN switching fabric interfaces to pseudo-ports, map pseudo-ports to WAN interfaces, and transmit LAN fabric datagrams received at the LAN switching fabric physical interface from the WAN physical interface via a mapped pseudo-port and a corresponding WAN interface.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 19, 2015
    Applicant: BAY MICROSYSTEMS, INC.
    Inventors: Robert Smedley, Soochon Radee, Suresh Shelvapille, Edward Kinzler, Richard Smedley, Joseph Senesi, Daniel Eigenbrode, John Wolf, Anunoy Ghosh, Gerard Jankauskas, Man Dieu Trinh
  • Patent number: 7411968
    Abstract: Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Simon Chong, Anguo Tony Huang, Man Dieu Trinh
  • Patent number: 7349403
    Abstract: A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: March 25, 2008
    Assignee: Bay Microsystems, Inc.
    Inventors: Barry Lee, Man Dieu Trinh
  • Patent number: 6996117
    Abstract: An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i.e., the time to complete a process is known) and that it employs a pipelined “multiple instruction single date” (“MISD”) architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 7, 2006
    Assignee: Bay Microsystems, Inc.
    Inventors: Barry Lee, Golchiro Ono, Man Dieu Trinh, Ryszard Bleszynski
  • Patent number: 6735773
    Abstract: The present invention provides techniques for controlling the functionality of a network processor and for facilitating integration of the network processor with a host system. Application programming interfaces (APIs) are provided which can be invoked by the host system for performing device level functions on the network processor. The APIs are provided by a device control module which may execute either on the host system or on the network processor. A host application may invoke an API and the function corresponding to the invoked API is performed by the network processor. Responses or results from the function execution may then be forwarded by the network processor to the host application.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventors: Man Dieu Trinh, Chi-Hua Chang, Srinivas Dabir
  • Patent number: 6724767
    Abstract: Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: April 20, 2004
    Assignee: Intel Corporation
    Inventors: Simon Chong, Anguo Tony Huang, Man Dieu Trinh
  • Patent number: 6708210
    Abstract: The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: March 16, 2004
    Assignee: Intel Corporation
    Inventors: Chi-Hua Chang, Man Dieu Trinh
  • Publication number: 20040028067
    Abstract: Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission.
    Type: Application
    Filed: August 7, 2003
    Publication date: February 12, 2004
    Applicant: SOFTCOM MICROSYSTEMS
    Inventors: Simon Chong, Anguo Tony Huang, Man Dieu Trinh
  • Publication number: 20030172147
    Abstract: The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.
    Type: Application
    Filed: March 13, 2003
    Publication date: September 11, 2003
    Applicant: SOFTCOM MICROSYSTEMS
    Inventors: Chi-Hua Chang, Man Dieu Trinh
  • Publication number: 20030152084
    Abstract: A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.
    Type: Application
    Filed: September 19, 2002
    Publication date: August 14, 2003
    Inventors: Barry Lee, Man Dieu Trinh
  • Publication number: 20030152076
    Abstract: An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i.e., the time to complete a process is known) and that it employs a pipelined “multiple instruction single date” (“MISD”) architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.
    Type: Application
    Filed: September 19, 2002
    Publication date: August 14, 2003
    Inventors: Barry Lee, Golchiro Ono, Man Dieu Trinh, Ryszard Bleszynski
  • Patent number: 6604136
    Abstract: The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: August 5, 2003
    Assignee: Intel Corporation
    Inventors: Chi-Hua Chang, Man Dieu Trinh
  • Patent number: 6311212
    Abstract: Systems and methods for storing, or caching, VC descriptors on a single-chip network processor to enhance system performance. The single-chip network processor includes an on-chip cache memory that stores VC descriptors for fast retrieval. When a VC descriptor is to be retrieved, a processing engine sends a VC descriptor identifier to a content-addressable memory (CAM), which stores VC descriptor identifiers in association with addresses in the cache where associated VC descriptors are stored. If the desired VC descriptor is stored in the cache, the CAM returns the associated address to the processing engine and the processing engine retrieves the VC descriptor from the cache memory. If the VC descriptor is not stored in the cache, the CAM returns a miss signal to the processing engine, and the processing engine retrieves the VC descriptor from an off-chip memory.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: October 30, 2001
    Assignee: Intel Corporation
    Inventors: Simon Chong, David A. Stelliga, Ryszard Bleszynski, Anguo Tony Huang, Man Dieu Trinh