Abstract: An exemplary shift register includes plural shift register units (S1˜Sn). All the shift register units receive either a first clock signal or a second clock signal, and the shift register units output a plurality of shift register signals in sequence. An output of a previous shift register unit is an input of the next adjacent shift register unit.

Abstract: An exemplary shift register (20) includes shift register units (S1˜Sn). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. An output of previous adjacent one of the shift register units is an input of the shift register unit.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. The outputs waveforms of pre-stage shift register unit and the rear-stage shift register unit have no overlapping signals.

Abstract: An exemplary gamma voltage output circuit (3) has an internal resistor string (31), which has a plurality of resistors and a plurality of nodes; at least one external resistor string (32, 33, 34), which has a plurality of resistors and a plurality of nodes; a plurality of switching circuit (35), each switching circuit having at least one input end (353, 354, 355) and at least one output end (356). The internal and the at least one external resistor strings connect in series between the power source AVDD and ground, respectively. Each node outputs a gamma voltage. The nodes of internal and the at least one external resistor strings respectively are connected to the output end and the input end, the resistors of the internal resistor string parallel connecting to corresponding resistors of the at least one external resistor string through the corresponding switching circuit.

Abstract: An exemplary driving circuit (250) of an LCD (200) includes: gate lines (210) that are parallel to each other and that each extend along a first direction; data lines (202) that are parallel to each other and that each extend along a second direction substantially orthogonal to the first direction; a gate driving circuit (210) connected to the gate lines; a data driving circuit (220) connected to the data lines; and a pre-charging voltage circuit (240). The pre-charging voltage circuit is configured to provide a pre-charging voltage to each of the data lines before the gate driving circuit scans the gate lines.

Abstract: An exemplary shift register includes plural shift register units (S1˜Sn). All the shift register units receive either a first clock signal or a second clock signal, and the shift register units output a plurality of shift register signals in sequence. An output of a previous shift register unit is an input of the next adjacent shift register unit.

Abstract: An exemplary shift register (20) includes shift register units (S1˜Sn). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. An output of previous adjacent one of the shift register units is an input of the shift register unit.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. The outputs waveforms of pre-stage shift register unit and the rear-stage shift register unit have no overlapping signals.

Abstract: An exemplary gamma voltage output circuit (3) has an internal resistor string (31), which has a plurality of resistors and a plurality of nodes; at least one external resistor string (32, 33, 34), which has a plurality of resistors and a plurality of nodes; a plurality of switching circuit (35), each switching circuit having at least one input end (353, 354, 355) and at least one output end (356). The internal and the at least one external resistor strings connect in series between the power source AVDD and ground, respectively. Each node outputs a gamma voltage. The nodes of internal and the at least one external resistor strings respectively are connected to the output end and the input end, the resistors of the internal resistor string parallel connecting to corresponding resistors of the at least one external resistor string through the corresponding switching circuit.

Abstract: An exemplary driving circuit (250) of an LCD (200) includes: gate lines (210) that are parallel to each other and that each extend along a first direction; data lines (202) that are parallel to each other and that each extend along a second direction substantially orthogonal to the first direction; a gate driving circuit (210) connected to the gate lines; a data driving circuit (220) connected to the data lines; and a pre-charging voltage circuit (240). The pre-charging voltage circuit is configured to provide a pre-charging voltage to each of the data lines before the gate driving circuit scans the gate lines.