Abstract: A parallel test board preferably includes a plurality of serial slots connected to a motherboard and a number of parallel slots connected to the motherboard in parallel with each other. The motherboard provides an actual operational environment for devices under test (DUTs). DUTs are mounted in the slots. Using a plurality of serial slots, distorted timings due to one serial slot (e.g., an extension slot) have an influence on the other serial slot (e.g., a reference slot), as well as on the parallel slots. In this manner, a timing margin failure occurring during a multi-bank operation can be effectively detected. The slots to which the DUTs are mounted preferably have a socket structure with a support block having contact pins arranged thereon. Each of the contact pins preferably has a module contact part configured to contact a tab of the DUT and a board contact part configured to contact conductive wiring patterns of an intermediation board.

Abstract: A parallel test board preferably includes a plurality of serial slots connected to a motherboard and a number of parallel slots connected to the motherboard in parallel with each other. The motherboard provides an actual operational environment for devices under test (DUTs). DUTs are mounted in the slots. Using a plurality of serial slots, distorted timings due to one serial slot (e.g., an extension slot) have an influence on the other serial slot (e.g., a reference slot), as well as on the parallel slots. In this manner, a timing margin failure occurring during a multi-bank operation can be effectively detected. The slots to which the DUTs are mounted preferably have a socket structure with a support block having contact pins arranged thereon. Each of the contact pins preferably has a module contact part configured to contact a tab of the DUT and a board contact part configured to contact conductive wiring patterns of an intermediation board.