Patents by Inventor Man Hoi Wong

Man Hoi Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10861945
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 8, 2020
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Man Hoi Wong, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Publication number: 20200144377
    Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 7, 2020
    Applicants: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Masataka HIGASHIWAKI, Yoshiaki NAKATA, Takafumi KAMIMURA, Man Hoi WONG, Kohei SASAKI, Daiki WAKIMOTO
  • Publication number: 20170288061
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, an undoped ?-Ga2O3-based single crystal layer formed on the high-resistivity substrate, and an n-type channel layer that includes a side surface surrounded by the undoped ?-Ga2O3-based single crystal layer. The undoped ?-Ga2O3-based single crystal layer includes an element isolation region.
    Type: Application
    Filed: August 6, 2015
    Publication date: October 5, 2017
    Inventors: Kohei SASAKI, Masataka HIGASHIWAKI, Man Hoi WONG
  • Publication number: 20170278933
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Application
    Filed: August 18, 2015
    Publication date: September 28, 2017
    Inventors: Kohei SASAKI, Ken GOTO, Masataka HIGASHIWAKI, Man Hoi WONG, Akinori KOUKITO, Yoshinao KUMAGAI, Hisashi MURAKAMI
  • Patent number: 8829567
    Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 9, 2014
    Assignee: Sematech, Inc.
    Inventors: Rinus Tek Po Lee, Tae Woo Kim, Man Hoi Wong, Richard Hill
  • Publication number: 20140183597
    Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: SEMATECH, INC.
    Inventors: Rinus Tek Po LEE, Tae Woo KIM, Man Hoi WONG, Richard HILL
  • Patent number: 8039352
    Abstract: A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: October 18, 2011
    Assignee: The Regents of the University of California
    Inventors: Umesh K. Mishra, Tomas A. Palacios Gutierrez, Man-Hoi Wong
  • Patent number: 7935985
    Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 3, 2011
    Assignee: The Regents of the University of Califonia
    Inventors: Umesh K. Mishra, Yi Pei, Siddharth Rajan, Man Hoi Wong
  • Publication number: 20090218599
    Abstract: A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.
    Type: Application
    Filed: May 27, 2008
    Publication date: September 3, 2009
    Applicant: The Regents of the University of California
    Inventors: Umesh K. Mishra, Tomas A. Palacios Gutierrez, Man Hoi Wong
  • Publication number: 20080237640
    Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Yi Pei, Siddharth Rajan, Man Hoi Wong