Patents by Inventor Manhsuan Lin

Manhsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Buffer layer structure to improve GaN semiconductors
    Patent number: 11705489
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 18, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • NOVEL BUFFER LAYER STRUCTURE TO IMPROVE GAN SEMICONDUCTORS
    Publication number: 20230215924
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Application
    Filed: March 9, 2023
    Publication date: July 6, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • NOVEL BUFFER LAYER STRUCTURE TO IMPROVE GAN SEMICONDUCTORS
    Publication number: 20190221648
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Application
    Filed: December 19, 2018
    Publication date: July 18, 2019
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Semiconductor heterostructures and methods for forming same
    Patent number: 10211297
    Abstract: A heterostructure includes a substrate; an intermediate layer disposed on the substrate; and a group III-V layer having a first primary surface disposed on the intermediate layer and a dopant concentration that varies in a manner including a plurality of ramps with at least one of increasing dopant concentration and decreasing dopant concentration, along the growth direction from the first primary surface throughout the layer's thickness before terminating in a second primary surface.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 19, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Manhsuan Lin
  • SEMICONDUCTOR HETEROSTRUCTURES AND METHODS FOR FORMING SAME
    Publication number: 20180323265
    Abstract: A heterostructure includes a substrate; an intermediate layer disposed on the substrate; and a group III-V layer having a first primary surface disposed on the intermediate layer and a dopant concentration that varies in a manner including a plurality of ramps with at least one of increasing dopant concentration and decreasing dopant concentration, along the growth direction from the first primary surface throughout the layer's thickness before terminating in a second primary surface.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 8, 2018
    Applicant: Global Wafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Manhsuan Lin
  • Silicon substrates with compressive stress and methods for production of the same
    Patent number: 9633843
    Abstract: A heterostructure may include a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and a deposition layer disposed on the second primary surface of the substrate. The heterostructure may further include an epitaxial layer disposed on the deposition layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 25, 2017
    Assignee: Global Wafers Co., Ltd
    Inventors: Yao-Chung Chang, Chia-Wen Ko, Manhsuan Lin
  • SILICON SUBSTRATES WITH COMPRESSIVE STRESS AND METHODS FOR PRODUCTION OF THE SAME
    Publication number: 20160307754
    Abstract: A heterostructure may include a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and a deposition layer disposed on the second primary surface of the substrate. The heterostructure may further include an epitaxial layer disposed on the deposition layer.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Applicant: Global Wafers Co., Ltd.
    Inventors: Yao-Chung Chang, Chia-Wen Ko, Manhsuan Lin