Abstract: Systems, devices, and methods for reducing Vpass disturb are provided. In one aspect, a semiconductor device includes a first deck and a second deck, each including memory cells coupled to corresponding word lines; and a peripheral circuit coupled to the memory array structure. For programming a first memory cell of the first deck, the peripheral circuit configured to: apply a first voltage to a first word line coupled to the first memory cell; apply a second voltage to a second word line of the first deck; apply a third voltage to a third word line between the first word line and a fourth word line of the second deck; and apply a fourth voltage to the fourth word line. The first voltage is greater than the second voltage, the second voltage is greater than the fourth voltage, and the fourth voltage is greater than the third voltage.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, memory cells, and a source select gate (SSG) transistor, a bit line coupled to the DSG transistors, a source line coupled to the SSG transistor, and a peripheral circuit coupled to the memory string through the bit line and the source line. The peripheral circuit is configured to, in a pre-charge period of a program operation, apply a bias voltage to at least one of the bit line or the source line. The bias voltage is determined based on a temperature associated with the memory device.

Abstract: Examples of the present disclosure provide a test device, a wafer, and a test method. The test device includes a control circuit connected to M groups of pads and N groups of test units, wherein M and N are both integers greater than 1; a number of test units included in each group of test units is less than or equal to M, and a total number of the test units is greater than M. The control circuit is configured to receive a test signal, select one of the N groups of test units based on the test signal, and connect at least some of the M groups of pads to the test units in the selected group of test units in one-to-one correspondence.

Abstract: Examples of the present application disclose a programming method for a memory device, a memory device and a memory system. The programming method includes: applying a programming voltage on a selected word line; applying a first pass voltage on a first word line adjacent to the selected word line; and applying a second pass voltage on a second word line adjacent to the selected word line, wherein the first pass voltage and the second pass voltage include at least two ramp phases, and the first pass voltage and the second pass voltage have different ramp timings in at least one ramp phase among other ramp phases after the first ramp phase, and the ramp timing is the timing when the voltage value starts to ramp up from a certain voltage value.

Abstract: A sleeve mold for a method of high-throughput hot isostatic pressing micro-synthesis for combinatorial materials includes a honeycomb-array-sleeve and an upper cover, wherein a plurality of single cells are tightly arranged inside the honeycomb-array-sleeve, an exhaust tube is arranged on the upper cover, after the single cells are filled with powder materials, the upper cover is sealed welding on the honeycomb-array-sleeve, and the honeycomb-array-sleeve and the upper cover are both integrally produced by additive manufacturing. According to the method and the sleeve mold, the powder metallurgy hot isostatic pressing process is utilized to prepare small-size bulk combinatorial materials with multiple discrete components rapidly at one time.

Abstract: The invention relates to a method of high-throughput hot isostatic pressing micro-synthesis for the combinatorial materials and a sleeve mould thereof. The sleeve mould (2) comprises a honeycomb-array-sleeve (3) and an upper cover (4), wherein a plurality of single cells (6) are tightly arranged inside the honeycomb-array-sleeve (3), an exhaust tube (5) is arranged on the upper cover (4), after the single cells (6) are filled with powder materials, the upper cover (4) is sealed welding on the honeycomb-array-sleeve (3), and the honeycomb-array-sleeve (3) and the upper cover (4) are both integrally produced by additive manufacturing. According to the method and the sleeve mould, the powder metallurgy hot isostatic pressing process is utilized to prepare small-size bulk combinatorial materials with multiple discrete components rapidly at one time. This method has the characteristics of high sintering speed, high compaction density, good thermal diffusivity, short production cycle and low material consumption.