Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

Abstract: Techniques, apparatus and systems are described for performing variable length decoding. In one aspect, a variable length decoding apparatus includes a first computation unit to determine whether a symbol corresponding to an input data is included in an upper group or a lower group of a variable length code tree. Responsive to the determination, when the symbol corresponding to the input data is included in the lower group, the first computation unit detects look-up table information corresponding to a subgroup that includes the symbol corresponding to the input data within the lower group that includes multiple subgroups. The variable length decoding apparatus includes a second computation unit to detect the symbol corresponding to the input data by searching a look-up table corresponding to the look-up table information when the look-up table information is received from the first computation unit.

Abstract: A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.

Abstract: Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.

Abstract: Techniques, apparatus and systems are described for performing variable length decoding. In one aspect, a variable length decoding apparatus includes a first computation unit to determine whether a symbol corresponding to an input data is included in an upper group or a lower group of a variable length code tree. Responsive to the determination, when the symbol corresponding to the input data is included in the lower group, the first computation unit detects look-up table information corresponding to a subgroup that includes the symbol corresponding to the input data within the lower group that includes multiple subgroups. The variable length decoding apparatus includes a second computation unit to detect the symbol corresponding to the input data by searching a look-up table corresponding to the look-up table information when the look-up table information is received from the first computation unit.

Abstract: Provided are a method and apparatus for sharing a memory of a multi-codec. For each of a plurality of codecs, the method and apparatus cluster a variable length code tree into a plurality of groups whereby a level difference between symbols in each group of the plurality of groups is less than a predetermined value, wherein the variable length code tree corresponds to at least one of variable length code tables for each of the plurality of codecs, refer to maximum levels of the symbols in each group of the plurality of groups, and determine a storage capacity of an internal memory shared between the variable length code tables for the plurality of codecs.

Abstract: A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.

Abstract: Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.