Patents by Inventor Man-jae YANG

Man-jae YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10937471
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20200349986
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10741225
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20200194040
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: DONG-SU JANG, MAN-JAE YANG, JEONG-DON IHM, GO-EUN JUNG, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Patent number: 10600454
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-su Jang, Man-jae Yang, Jeong-don Ihm, Go-eun Jung, Byung-hoon Jeong, Young-don Choi
  • Publication number: 20190096447
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Application
    Filed: May 9, 2018
    Publication date: March 28, 2019
    Inventors: DONG-SU JANG, Man-jae YANG, Jeong-don IHM, Go-eun JUNG, Byung-hoon JEONG, Young-don CHOI