Patents by Inventor Man-Jong Yu

Man-Jong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10444621
    Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Man-Jong Yu
  • Publication number: 20180252997
    Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.
    Type: Application
    Filed: May 3, 2018
    Publication date: September 6, 2018
    Inventor: Man-Jong Yu
  • Publication number: 20180004080
    Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.
    Type: Application
    Filed: September 19, 2017
    Publication date: January 4, 2018
    Inventor: Man-Jong Yu
  • Patent number: 9798227
    Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Man-Jong Yu
  • Publication number: 20160233103
    Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.
    Type: Application
    Filed: July 17, 2015
    Publication date: August 11, 2016
    Inventor: Man-Jong Yu
  • Patent number: 9178051
    Abstract: A semiconductor device includes an active region on a semiconductor substrate. The active region is defined by a device isolation layer and includes gate-recesses. The semiconductor device further includes gate electrodes in the gate-recesses, a contact recess in the active region between the gate-recesses, a cell pad that covers at least a portion of the active region between the gate-recesses and that fills at least a portion of the contact recess, and a bit line electrically connected to the cell pad.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: November 3, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Man-jong Yu
  • Publication number: 20120267712
    Abstract: A semiconductor device includes an active region on a semiconductor substrate. The active region is defined by a device isolation layer and includes gate-recesses. The semiconductor device further includes gate electrodes in the gate-recesses, a contact recess in the active region between the gate-recesses, a cell pad that covers at least a portion of the active region between the gate-recesses and that fills at least a portion of the contact recess, and a bit line electrically connected to the cell pad.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 25, 2012
    Inventor: Man-jong YU
  • Patent number: 8222715
    Abstract: A semiconductor device includes an insulation interlayer and an etch stop layer sequentially stacked on a substrate wherein a lower structure including a first contact pad is formed. A second contact pad penetrates the insulation interlayer and the etch stop layer and is connected to the first contact pad. The second contact pad protrudes from the etch stop layer. A pad spacer is provided between the second contact pad and the insulation interlayer. A lower electrode is provided on the etch stop layer and is connected to the second contact pad. A dielectric layer and an upper electrode are sequentially provided on the lower electrode.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: July 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Man-Jong Yu
  • Patent number: 8053831
    Abstract: A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Man-Jong Yu
  • Publication number: 20100244191
    Abstract: A semiconductor device includes an insulation interlayer and an etch stop layer sequentially stacked on a substrate wherein a lower structure including a first contact pad is formed. A second contact pad penetrates the insulation interlayer and the etch stop layer and is connected to the first contact pad. The second contact pad protrudes from the etch stop layer. A pad spacer is provided between the second contact pad and the insulation interlayer. A lower electrode is provided on the etch stop layer and is connected to the second contact pad. A dielectric layer and an upper electrode are sequentially provided on the lower electrode.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 30, 2010
    Inventor: Man-Jong YU
  • Patent number: 7633136
    Abstract: A semiconductor device includes an interlayer insulating film on a substrate. A runner part includes a plurality of runner lines spaced apart from each other by a regular interval under the interlayer insulating film. A fuse cut part includes a plurality of fuse lines spaced apart from each other by a wider interval than the interval between the runner lines. A via in the interlayer insulating film connects a fuse line and a runner line to each other.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: December 15, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Man-Jong Yu
  • Publication number: 20090020808
    Abstract: A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material.
    Type: Application
    Filed: May 20, 2008
    Publication date: January 22, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Man-Jong Yu
  • Publication number: 20070126077
    Abstract: A semiconductor device includes an interlayer insulating film on a substrate. A runner part includes a plurality of runner lines spaced apart from each other by a regular interval under the interlayer insulating film. A fuse cut part includes a plurality of fuse lines spaced apart from each other by a wider interval than the interval between the runner lines. A via in the interlayer insulating film connects a fuse line and a runner line to each other.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 7, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Man-Jong Yu
  • Publication number: 20060255391
    Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.
    Type: Application
    Filed: July 24, 2006
    Publication date: November 16, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Beom KIM, Won-Mo PARK, Yun-Jae LEE, Joon-Mo KWON, Myoung-Hee HAN, Man-Jong YU
  • Patent number: 7101769
    Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu
  • Publication number: 20040159909
    Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 19, 2004
    Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu