Patents by Inventor Man-Ju Lee

Man-Ju Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reconfigurable pin-to-pin interface capable of supporting different lane combinations and/or different physical layers and associated method
    Patent number: 10506139
    Abstract: A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 10, 2019
    Assignee: MEDIATEK INC.
    Inventors: Li-Hung Chiueh, Man-Ju Lee, Chen-Yu Hsiao, Ching-Hsiang Chang
  • RECONFIGURABLE PIN-TO-PIN INTERFACE CAPABLE OF SUPPORTING DIFFERENT LANE COMBINATIONS AND/OR DIFFERENT PHYSICAL LAYERS AND ASSOCIATED METHOD
    Publication number: 20190045090
    Abstract: A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.
    Type: Application
    Filed: July 3, 2018
    Publication date: February 7, 2019
    Inventors: Li-Hung Chiueh, Man-Ju Lee, Chen-Yu Hsiao