Abstract: A method for designing a driver including matching stages having transistors matched to each other is disclosed, including interpreting an offset caused by a mismatched characteristic difference of a plurality of transistors using a current change in a matching stage. A size of the transistors may be determined using the results of interpreting of the offset, and the size may be adjusted until a simulated yield of the driver obtained by a simulation using measured matching information and the determined size of the transistors approximates a targeted yield. The resulting determined size may be used to fabricate the driver, to obtain a test yield of the manufactured driver. If the test yield is not the targeted yield, the measured matching information may be adjusted until the adjusted yield of the driver obtained by the simulation approximates the test yield.

Abstract: A display includes a timing controller and a source driver. The timing controller reflects a rule making a frame recognizable on a signal different from a gate start pulse (GSP) informing of a start of the frame and transmits the rule-reflected signal. The source driver receives the rule-reflected signal transmitted from the timing controller and checks the rule reflected on the rule-reflected signal to thereby recognize the frame. The rule is reflected on the signal different from the GSP to inform of frame start or frame change and the rule-reflected signal is transmitted to the source driver. Using the rule, the source driver can recognize frame start or frame change. Accordingly, there is an effect of eliminating a necessity of a change in hardware resources or provision of an additional hardware resource in the source driver for the recognition of frame start or frame change.

Abstract: A signal generation apparatus for a liquid crystal display device includes a pingpong frame controller (PFC) for generating and outputting a signal alternating at intervals of two frames using a signal having a blank period for discrimination between frames, a pingpong line controller (PLC) for generating and outputting a signal alternating at intervals of two lines using the signal having the blank period, and a pingpong control (PPC) signal generator for performing a logic operation with respect to the output signal from the PLC and the output signal from the PFC to generate a pingpong control signal. Therefore, it is possible to generate the pingpong control signal for offset removal without an additional wiring for a frame indication signal on a PCB, thereby not only curtailing a production cost, but also reducing circuit complexity and providing a picture of excellent quality.

Abstract: A method for designing a driver including matching stages having transistors matched to each other is disclosed, including interpreting an offset caused by a mismatched characteristic difference of a plurality of transistors using a current change in a matching stage. A size of the transistors may be determined using the results of interpreting of the offset, and the size may be adjusted until a simulated yield of the driver obtained by a simulation using measured matching information and the determined size of the transistors approximates a targeted yield. The resulting determined size may be used to fabricate the driver, to obtain a test yield of the manufactured driver. If the test yield is not the targeted yield, the measured matching information may be adjusted until the adjusted yield of the driver obtained by the simulation approximates the test yield.

Abstract: A driving circuit for Liquid Crystal Display (LCD) device includes a unity-gain operation amplifier (OP amp), three switches, and two capacitors. The unity-gain OP amp buffers and carries a signal voltage on a transmission line. The first switch switches a connection between a noninverting terminal of the unity-gain OP amp and an input line of the signal voltage. One end of the second switch is connected to the input line of the signal voltage. One end of the third switch is connected to the noninverting terminal of the unity-gain OP amp. The first capacitor is connected between the other end of the third switch and the other end of the second switch. The second capacitor is connected between the other end of the first capacitor and the ground voltage terminal.

Abstract: A frequency synthesizer for generating a multiple tone lightwave signal that can be converted into an RF carrier or local oscillator signal. The frequency synthesizer comprises a multiple mode master laser, two slave lasers injection-locked to the master laser, an optical coupler coupling the optical outputs of the two slave lasers, which produces an optical heterodyne output. The frequency synthesizer further comprises a homodyne phase-lock loop providing feedback control over one of the slave lasers and a heterodyne phase-lock loop providing feedback control over the other slave laser. A local oscillator selector is used to select the optical mode to which one of the slave lasers is locked, thus providing selection of the frequencies of the heterodyne output.

Abstract: A frequency synthesizer for generating a multiple tone lightwave signal that can be converted into an RF carrier or local oscillator signal. The frequency synthesizer comprises a multiple mode master laser, two slave lasers injection-locked to the master laser, an optical coupler coupling the optical outputs of the two slave lasers, which produces an optical heterodyne output. The frequency synthesizer further comprises a homodyne phase-lock loop providing feedback control over one of the slave lasers and a heterodyne phase-lock loop providing feedback control over the other slave laser. A local oscillator selector is used to select the optical mode to which one of the slave lasers is locked, thus providing selection of the frequencies of the heterodyne output.

Abstract: A low phase noise oscillator 10 having a balanced feedback transformer 24 and a push-pull resonant circuit 12 for generating an oscillation excitation signal. The resonant circuit 12 is loaded by an output buffer 20 connected between first and second feedback terminals 16 and 18. The feedback transformer 24 provides first and second feedback paths of opposite phase polarity which link the resonant circuit 12 with the first and second feedback terminals 16 and 18.