Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o

Abstract: The present invention discloses a novel insulating layer for use in semiconductor devices, the insulating layer having a multi-layer nanolaminate structure consisting of alternating boron nitride thin films and silicon nitride thin films, each of a controlled, desired thickness, together with methods for forming the same. The insulating layer of the present invention has a multi-layer nanolaminate structure consisting of alternating boron nitride thin films and silicon nitride thin filmsformed by the steps of: (a) depositing a silicon nitride thin film on a wafer, (b) depositing a boron nitride thin film on the silicon nitride thin film, and (c) forming the multi-layer nanolaminate thin film by alternately repeating steps (a) and (b).

Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o

Abstract: A semiconductor memory device having a floating gate and a method of manufacturing the same, where a conductive layer for a floating gate is deposited on a semiconductor substrate and etched to form a conductive layer pattern. An annealing of the semiconductor substrate is carried out in an ambient atmosphere of hydrogen gas. Alternatively, an entire surface of the conductive layer pattern is etched by a dry etching method or a wet etching method. As a result, at least one edge of the conductive layer pattern is rounded, which reduces the likelihood that an electric field is concentrated at the edge and reduces a likelihood that the dielectric layer formed on the floating gate is thinner at the edge.

Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o

Abstract: The present invention discloses a novel insulating layer for use in semiconductor devices, the insulating layer having a multi-layer nanolaminate structure consisting of alternating boron nitride thin films and silicon nitride thin films, each of a controlled, desired thickness, together with methods for forming the same.

Abstract: Disclosed is a method for depositing a tungsten silicide layer on a wafer coated with a polysilicon layer in a CVD process chamber. A surface of the polysilicon layer is pre-treated by introducing a hydrogen compound gas including any elements among group III elements or group V elements of the periodic table into the CVD process chamber. The tungsten silicide layer is deposited on the polysilicon layer by introducing a silane source gas and a tungsten source gas into the CVD process chamber. Since the surface of the polysilicon layer is pre-treated using the hydrogen compound gas before the tungsten silicide layer is deposited on the polysilicon layer, void generation is prevented on an interfacial surface between the tungsten silicide layer and the polysilicon layer.

Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o

Abstract: A semiconductor memory device having a floating gate and a method of manufacturing the same, where a conductive layer for a floating gate is deposited on a semiconductor substrate and etched to form a conductive layer pattern. An annealing of the semiconductor substrate is carried out in an ambient atmosphere of hydrogen gas. Alternatively, an entire surface of the conductive layer pattern is etched by a dry etching method or a wet etching method. As a result, at least one edge of the conductive layer pattern is rounded, which reduces the likelihood that an electric field is concentrated at the edge and reduces a likelihood that the dielectric layer formed on the floating gate is thinner at the edge.

Abstract: Disclosed is a method for depositing a tungsten suicide layer on a wafer coated with a polysilicon layer in a CVD process chamber. A surface of the polysilicon layer is pre-treated by introducing a hydrogen compound gas including any elements among group III elements or group V elements of the periodic table into the CVD process chamber. The tungsten silicide layer is deposited on the polysilicon layer by introducing a silane source gas and a tungsten source gas into the CVD process chamber. Since the surface of the polysilicon layer is pre-treated using the hydrogen compound gas before the tungsten silicide layer is deposited on the polysilicon layer, void generation is prevented on an interfacial surface between the tungsten silicide layer and the polysilicon layer.

Abstract: A method of self-aligned shallow trench isolation and a method of manufacturing a non-volatile memory using the same are disclosed. An oxide layer, a first silicon layer and a nitride layer are successively formed on a semiconductor substrate. By using a single mask, the nitride layer, first silicon layer and oxide layer are etched to form an oxide layer pattern, a first silicon layer pattern and a nitride layer pattern. Subsequently, the upper portion of the substrate adjacent to the first silicon layer pattern is etched to a trench. The first silicon layer pattern and substrate are selectively etched to protrude the oxide layer pattern. The inner surface of the trench is oxidized to form a trench thermal oxide layer. Finally, a field oxide layer that fills up the trench is formed. Since the present invention prevents the sidewalls of the first silicon layer pattern from having a positive slope, a silicon residue does not remain during a subsequent gate etching process.

Abstract: A method for forming an integrated circuit capacitor includes the steps of forming a first electrode layer on a substrate wherein the first electrode has a first dopant concentration, and forming a second electrode layer on the first electrode layer opposite the substrate. The second electrode layer has a second dopant concentration different from the first dopant concentration. In addition, a portion of the second electrode layer is converted to a hemispherical grain layer. More particularly, the first dopant concentration is greater than the second dopant concentration. Related structures are also discussed.

Abstract: A silicon layer is formed on an integrated circuit substrate using silane and disilane thereby increasing a step coverage for the silicon layer, increasing a deposition rate for the silicon layer, reducing variability of the deposition rate, and reducing local crystallization of the silicon layer. More particularly, the step of forming the silicon layer can include forming a first silicon sublayer on the substrate using a first source gas including silane, and forming a second silicon sublayer on the first silicon sublayer using a second source gas different from the first source gas wherein the second source gas includes disilane. Alternately, the step of forming the silicon layer can include forming the silicon layer on the integrated circuit substrate using a source gas including a mixture of silane and disilane.