Patents by Inventor Mansun John Chan

Mansun John Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
    Patent number: 6300649
    Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: October 9, 2001
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
  • Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
    Patent number: 6121077
    Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: September 19, 2000
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
  • Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
    Patent number: 5982003
    Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: November 9, 1999
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko