Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.

Abstract: A diagnostic ultrasound system has a 2D array transducer which is operated with 1×N patches, patches which are only a single element wide. The “N” length of the patches extends in the elevation direction of a scanned 2D image plane, with the single element width extending in the lateral (azimuth) direction. Focusing is done along each patch in the elevation direction by a microbeamformer, and focusing in the lateral (azimuth) direction is done by the system beamformer. The minimal width of each patch in the azimuth direction enables the production of images highly resolved in the azimuthal plane of a 2D image, including the reception of highly resolved multilines for high frame rate imaging.

Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.

Abstract: Disclosed in the present application is a self-heating structure and a battery pack including the same. The self-heating structure includes a heating member, including a heating body and a connection lead molded on the heating body, the connection lead being used for electrically connecting a positive electrode tab of a core pack or a negative electrode tab of the core pack, so that a self-heating circuit is formed by the heating member and the core pack; and a control unit, controlling an on/off switching of the self-heating circuit according to temperature of the core pack, the control unit being provided on the connection lead to integrate the control unit and the connection lead.

Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.

Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.

Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.

Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.

Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.

Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.

Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.

Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.

Abstract: A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal.

Abstract: A pixel circuit includes four transistors, two capacitors and a light emitting element. A gate of first transistor receives a scan signal and a source/drain thereof receives a display data. A terminal of first capacitor couples to another source/drain of first transistor. A gate and a source/drain of second transistor couple to another terminal of first capacitor; and another source/drain thereof receives a switch signal. A terminal of second capacitor receives a reset signal; and another terminal thereof couples to another terminal of first capacitor. A gate of third transistor couples to a terminal of first capacitor. A gate of fourth transistor receives an enable signal; a source/drain thereof couples to a first power supply voltage; and another source/drain thereof couples to one source/drain of third transistor. The anode and cathode of the light emitting element couple to one source/drain of third transistor and a second power supply voltage, respectively.

Abstract: A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal.

Abstract: A pixel circuit includes four transistors, two capacitors and a light emitting element. A gate of first transistor receives a scan signal and a source/drain thereof receives a display data. A terminal of first capacitor couples to another source/drain of first transistor. A gate and a source/drain of second transistor couple to another terminal of first capacitor; and another source/drain thereof receives a switch signal. A terminal of second capacitor receives a reset signal; and another terminal thereof couples to another terminal of first capacitor. A gate of third transistor couples to a terminal of first capacitor. A gate of fourth transistor receives an enable signal; a source/drain thereof couples to a first power supply voltage; and another source/drain thereof couples to one source/drain of third transistor. The anode and cathode of the light emitting element couple to one source/drain of third transistor and a second power supply voltage, respectively.

Abstract: An impact-warning and prevention device in the shape of a license plate holder is disclosed, where some strong LED lights will be activated to shine focused light at the driver in the aft vehicle, so that the aft driver gets sufficient warning for slowing down or keeping a safer distance, if the aft vehicle is coming too close to the vehicle equipped with device of present application.